1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
|
/*
* include/asm-sh/cpu-sh3/cache.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_CACHE_H
#define __ASM_CPU_SH3_CACHE_H
#define L1_CACHE_BYTES 16
#define CCR 0xffffffec /* Address of Cache Control Register */
#define CCR_CACHE_CE 0x01 /* Cache Enable */
#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
#define CCR_CACHE_CF 0x08 /* Cache Flush */
#define CCR_CACHE_ORA 0x20 /* RAM mode */
#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
#define CACHE_PHYSADDR_MASK 0x1ffffc00
#define CCR_CACHE_ENABLE CCR_CACHE_CE
#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
#endif /* __ASM_CPU_SH3_CACHE_H */
|
