1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2013 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
*/
#ifndef __MIPS_ASM_SMP_CPS_H__
#define __MIPS_ASM_SMP_CPS_H__
#ifndef __ASSEMBLY__
struct vpe_boot_config {
unsigned long pc;
unsigned long sp;
unsigned long gp;
};
struct core_boot_config {
atomic_t vpe_mask;
struct vpe_boot_config *vpe_config;
};
extern struct core_boot_config *mips_cps_core_bootcfg;
extern void mips_cps_core_entry(void);
extern void mips_cps_core_init(void);
extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe);
extern void mips_cps_pm_save(void);
extern void mips_cps_pm_restore(void);
#ifdef CONFIG_MIPS_CPS
extern bool mips_cps_smp_in_use(void);
#else /* !CONFIG_MIPS_CPS */
static inline bool mips_cps_smp_in_use(void) { return false; }
#endif /* !CONFIG_MIPS_CPS */
#else /* __ASSEMBLY__ */
.extern mips_cps_bootcfg;
#endif /* __ASSEMBLY__ */
#endif /* __MIPS_ASM_SMP_CPS_H__ */
|
