1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Calxeda DDR memory controller
description: |
The Calxeda DDR memory controller is initialised and programmed by the
firmware, but an OS might want to read its registers for error reporting
purposes and to learn about the DRAM topology.
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
compatible:
enum:
- calxeda,hb-ddr-ctrl
- calxeda,ecx-2000-ddr-ctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
memory-controller@fff00000 {
compatible = "calxeda,hb-ddr-ctrl";
reg = <0xfff00000 0x1000>;
interrupts = <0 91 4>;
};
|
