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|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/amlogic,c3-reset.h>
#include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
#include <dt-bindings/clock/amlogic,c3-scmi-clkc.h>
#include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
#include <dt-bindings/power/amlogic,c3-pwrc.h>
#include <dt-bindings/gpio/amlogic-c3-gpio.h>
/ {
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
sm: secure-monitor {
compatible = "amlogic,meson-gxbb-sm";
pwrc: power-controller {
compatible = "amlogic,c3-pwrc";
#power-domain-cells = <1>;
};
};
sram@7f50e00 {
compatible = "mmio-sram";
reg = <0x0 0x07f50e00 0x0 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x07f50e00 0x100>;
scmi_shmem: sram@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x100>;
};
};
firmware {
scmi: scmi {
compatible = "arm,scmi-smc";
arm,smc-id = <0x820000C1>;
shmem = <&scmi_shmem>;
#address-cells = <1>;
#size-cells = <0>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@fff01000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xfff01000 0 0x1000>,
<0x0 0xfff02000 0 0x2000>,
<0x0 0xfff04000 0 0x2000>,
<0x0 0xfff06000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
apb4: bus@fe000000 {
compatible = "simple-bus";
reg = <0x0 0xfe000000 0x0 0x480000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
clkc_periphs: clock-controller@0 {
compatible = "amlogic,c3-peripherals-clkc";
reg = <0x0 0x0 0x0 0x49c>;
#clock-cells = <1>;
clocks = <&xtal>,
<&scmi_clk CLKID_OSC>,
<&scmi_clk CLKID_FIXED_PLL_OSC>,
<&clkc_pll CLKID_FCLK_DIV2>,
<&clkc_pll CLKID_FCLK_DIV2P5>,
<&clkc_pll CLKID_FCLK_DIV3>,
<&clkc_pll CLKID_FCLK_DIV4>,
<&clkc_pll CLKID_FCLK_DIV5>,
<&clkc_pll CLKID_FCLK_DIV7>,
<&clkc_pll CLKID_GP0_PLL>,
<&scmi_clk CLKID_GP1_PLL_OSC>,
<&clkc_pll CLKID_HIFI_PLL>,
<&scmi_clk CLKID_SYS_CLK>,
<&scmi_clk CLKID_AXI_CLK>,
<&scmi_clk CLKID_SYS_PLL_DIV16>,
<&scmi_clk CLKID_CPU_CLK_DIV16>;
clock-names = "xtal_24m",
"oscin",
"fix",
"fdiv2",
"fdiv2p5",
"fdiv3",
"fdiv4",
"fdiv5",
"fdiv7",
"gp0",
"gp1",
"hifi",
"sysclk",
"axiclk",
"sysplldiv16",
"cpudiv16";
};
reset: reset-controller@2000 {
compatible = "amlogic,c3-reset";
reg = <0x0 0x2000 0x0 0x98>;
#reset-cells = <1>;
};
watchdog@2100 {
compatible = "amlogic,c3-wdt", "amlogic,t7-wdt";
reg = <0x0 0x2100 0x0 0x10>;
clocks = <&xtal>;
};
periphs_pinctrl: pinctrl@4000 {
compatible = "amlogic,c3-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x4000 0x0 0x02de>;
gpio: bank@0 {
reg = <0x0 0x0 0x0 0x004c>,
<0x0 0x100 0x0 0x01de>;
reg-names = "mux", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 0 55>;
};
i2c0_pins1: i2c0-pins1 {
mux {
groups = "i2c0_sda_e",
"i2c0_scl_e";
function = "i2c0";
bias-disable;
drive-strength-microamp = <3000>;
};
};
i2c0_pins2: i2c0-pins2 {
mux {
groups = "i2c0_sda_d",
"i2c0_scl_d";
function = "i2c0";
bias-disable;
drive-strength-microamp = <3000>;
};
};
i2c1_pins1: i2c1-pins1 {
mux {
groups = "i2c1_sda_x",
"i2c1_scl_x";
function = "i2c1";
bias-disable;
drive-strength-microamp = <3000>;
};
};
i2c1_pins2: i2c1-pins2 {
mux {
groups = "i2c1_sda_d",
"i2c1_scl_d";
function = "i2c1";
bias-disable;
drive-strength-microamp = <3000>;
};
};
i2c1_pins3: i2c1-pins3 {
mux {
groups = "i2c1_sda_a",
"i2c1_scl_a";
function = "i2c1";
bias-disable;
drive-strength-microamp = <3000>;
};
};
i2c1_pins4: i2c1-pins4 {
mux {
groups = "i2c1_sda_b",
"i2c1_scl_b";
function = "i2c1";
bias-disable;
drive-strength-microamp = <3000>;
};
};
i2c2_pins1: i2c2-pins1 {
mux {
groups = "i2c2_sda",
"i2c2_scl";
function = "i2c2";
bias-disable;
drive-strength-microamp = <3000>;
};
};
i2c3_pins1: i2c3-pins1 {
mux {
groups = "i2c3_sda_c",
"i2c3_scl_c";
function = "i2c3";
bias-disable;
drive-strength-microamp = <3000>;
};
};
i2c3_pins2: i2c3-pins2 {
mux {
groups = "i2c3_sda_x",
"i2c3_scl_x";
function = "i2c3";
bias-disable;
drive-strength-microamp = <3000>;
};
};
i2c3_pins3: i2c3-pins3 {
mux {
groups = "i2c3_sda_d",
"i2c3_scl_d";
function = "i2c3";
bias-disable;
drive-strength-microamp = <3000>;
};
};
nand_pins: nand-pins {
mux {
groups = "emmc_nand_d0",
"emmc_nand_d1",
"emmc_nand_d2",
"emmc_nand_d3",
"emmc_nand_d4",
"emmc_nand_d5",
"emmc_nand_d6",
"emmc_nand_d7",
"nand_ce0",
"nand_ale",
"nand_cle",
"nand_wen_clk",
"nand_ren_wr";
function = "nand";
input-enable;
};
};
sdcard_pins: sdcard-pins {
mux {
groups = "sdcard_d0",
"sdcard_d1",
"sdcard_d2",
"sdcard_d3",
"sdcard_clk",
"sdcard_cmd";
function = "sdcard";
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
sdcard_clk_gate_pins: sdcard-clk-cmd-pins {
mux {
groups = "GPIOC_4";
function = "gpio_periphs";
bias-pull-down;
drive-strength-microamp = <4000>;
};
};
sdio_m_clk_gate_pins: sdio-m-clk-cmd-pins {
mux {
groups = "sdio_clk";
function = "sdio";
bias-pull-down;
drive-strength-microamp = <4000>;
};
};
sdio_m_pins: sdio-m-all-pins {
mux {
groups = "sdio_d0",
"sdio_d1",
"sdio_d2",
"sdio_d3",
"sdio_clk",
"sdio_cmd";
function = "sdio";
input-enable;
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
spicc0_pins1: spicc0-pins1 {
mux {
groups = "spi_a_mosi_b",
"spi_a_miso_b",
"spi_a_clk_b";
function = "spi_a";
drive-strength-microamp = <3000>;
};
};
spicc0_pins2: spicc0-pins2 {
mux {
groups = "spi_a_mosi_c",
"spi_a_miso_c",
"spi_a_clk_c";
function = "spi_a";
drive-strength-microamp = <3000>;
};
};
spicc0_pins3: spicc0-pins3 {
mux {
groups = "spi_a_mosi_x",
"spi_a_miso_x",
"spi_a_clk_x";
function = "spi_a";
drive-strength-microamp = <3000>;
};
};
spicc1_pins1: spicc1-pins1 {
mux {
groups = "spi_b_mosi_d",
"spi_b_miso_d",
"spi_b_clk_d";
function = "spi_b";
drive-strength-microamp = <3000>;
};
};
spicc1_pins2: spicc1-pins2 {
mux {
groups = "spi_b_mosi_x",
"spi_b_miso_x",
"spi_b_clk_x";
function = "spi_b";
drive-strength-microamp = <3000>;
};
};
spifc_pins: spifc-pins {
mux {
groups = "spif_mo",
"spif_mi",
"spif_clk",
"spif_cs",
"spif_hold",
"spif_wp",
"spif_clk_loop";
function = "spif";
drive-strength-microamp = <4000>;
};
};
};
gpio_intc: interrupt-controller@4080 {
compatible = "amlogic,c3-gpio-intc", "amlogic,meson-gpio-intc";
reg = <0x0 0x4080 0x0 0x0020>;
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts =
<10 11 12 13 14 15 16 17 18 19 20 21>;
};
clkc_pll: clock-controller@8000 {
compatible = "amlogic,c3-pll-clkc";
reg = <0x0 0x8000 0x0 0x1a4>;
#clock-cells = <1>;
clocks = <&scmi_clk CLKID_TOP_PLL_OSC>,
<&scmi_clk CLKID_MCLK_PLL_OSC>,
<&scmi_clk CLKID_FIXED_PLL_OSC>;
clock-names = "top",
"mclk",
"fix";
};
eth_phy: mdio-multiplexer@28000 {
compatible = "amlogic,g12a-mdio-mux";
reg = <0x0 0x28000 0x0 0xa4>;
clocks = <&clkc_periphs CLKID_SYS_ETH_PHY>,
<&xtal>,
<&clkc_pll CLKID_FCLK_50M>;
clock-names = "pclk", "clkin0", "clkin1";
mdio-parent-bus = <&mdio0>;
#address-cells = <1>;
#size-cells = <0>;
ext_mdio: mdio@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
int_mdio: mdio@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
internal_ephy: ethernet_phy@8 {
compatible = "ethernet-phy-id0180.3301",
"ethernet-phy-ieee802.3-c22";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
reg = <8>;
max-speed = <100>;
};
};
};
spicc0: spi@50000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0x50000 0x0 0x44>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc_periphs CLKID_SYS_SPICC_0>,
<&clkc_periphs CLKID_SPICC_A>;
clock-names = "core", "pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spicc1: spi@52000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0x52000 0x0 0x44>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc_periphs CLKID_SYS_SPICC_1>,
<&clkc_periphs CLKID_SPICC_B>;
clock-names = "core", "pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spifc: spi@56000 {
compatible = "amlogic,a1-spifc";
reg = <0x0 0x56000 0x0 0x290>;
interrupts = <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_periphs CLKID_SPIFC>;
clock-names = "core";
status = "disabled";
};
i2c0: i2c@66000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x66000 0x0 0x24>;
interrupts = <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc_periphs CLKID_SYS_I2C_M_A>;
status = "disabled";
};
i2c1: i2c@68000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x68000 0x0 0x24>;
interrupts = <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc_periphs CLKID_SYS_I2C_M_B>;
status = "disabled";
};
i2c2: i2c@6a000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x6a000 0x0 0x24>;
interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc_periphs CLKID_SYS_I2C_M_C>;
status = "disabled";
};
i2c3: i2c@6c000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x6c000 0x0 0x24>;
interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc_periphs CLKID_SYS_I2C_M_D>;
status = "disabled";
};
uart_b: serial@7a000 {
compatible = "amlogic,meson-s4-uart",
"amlogic,meson-ao-uart";
reg = <0x0 0x7a000 0x0 0x18>;
interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&xtal>, <&clkc_periphs CLKID_SYS_UART_B>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};
sec_ao: ao-secure@10220 {
compatible = "amlogic,c3-ao-secure",
"amlogic,meson-gx-ao-secure",
"syscon";
reg = <0x0 0x10220 0x0 0x140>;
amlogic,has-chip-id;
};
sdio: mmc@88000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0x88000 0x0 0x800>;
interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
power-domains = <&pwrc PWRC_C3_SDIOA_ID>;
clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_A>,
<&clkc_periphs CLKID_SD_EMMC_A>,
<&clkc_pll CLKID_FCLK_DIV2>;
clock-names = "core","clkin0", "clkin1";
no-mmc;
no-sd;
resets = <&reset RESET_SD_EMMC_A>;
status = "disabled";
};
sd: mmc@8a000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0x8a000 0x0 0x800>;
interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
power-domains = <&pwrc PWRC_C3_SDCARD_ID>;
clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>,
<&clkc_periphs CLKID_SD_EMMC_B>,
<&clkc_pll CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
no-mmc;
no-sdio;
resets = <&reset RESET_SD_EMMC_B>;
status = "disabled";
};
nand: nand-controller@8d000 {
compatible = "amlogic,meson-axg-nfc";
reg = <0x0 0x8d000 0x0 0x200>,
<0x0 0x8C000 0x0 0x4>;
reg-names = "nfc", "emmc";
interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>,
<&clkc_pll CLKID_FCLK_DIV2>;
clock-names = "core", "device";
status = "disabled";
};
};
ethmac: ethernet@fdc00000 {
compatible = "amlogic,meson-g12a-dwmac",
"snps,dwmac-3.70a",
"snps,dwmac";
reg = <0x0 0xfdc00000 0x0 0x10000>,
<0x0 0xfe024000 0x0 0x8>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
power-domains = <&pwrc PWRC_C3_ETH_ID>;
clocks = <&clkc_periphs CLKID_SYS_ETH_MAC>,
<&clkc_pll CLKID_FCLK_DIV2>,
<&clkc_pll CLKID_FCLK_50M>;
clock-names = "stmmaceth", "clkin0", "clkin1";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
status = "disabled";
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
};
};
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