1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2019 Intel Corporation
*/
#ifndef __INTEL_DE_H__
#define __INTEL_DE_H__
#include "intel_display_core.h"
#include "intel_dmc_wl.h"
#include "intel_dsb.h"
#include "intel_uncore.h"
#include "intel_uncore_trace.h"
static inline struct intel_uncore *__to_uncore(struct intel_display *display)
{
return to_intel_uncore(display->drm);
}
static inline u32
intel_de_read(struct intel_display *display, i915_reg_t reg)
{
u32 val;
intel_dmc_wl_get(display, reg);
val = intel_uncore_read(__to_uncore(display), reg);
intel_dmc_wl_put(display, reg);
return val;
}
static inline u8
intel_de_read8(struct intel_display *display, i915_reg_t reg)
{
u8 val;
intel_dmc_wl_get(display, reg);
val = intel_uncore_read8(__to_uncore(display), reg);
intel_dmc_wl_put(display, reg);
return val;
}
static inline u64
intel_de_read64_2x32(struct intel_display *display,
i915_reg_t lower_reg, i915_reg_t upper_reg)
{
u64 val;
intel_dmc_wl_get(display, lower_reg);
intel_dmc_wl_get(display, upper_reg);
val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg,
upper_reg);
intel_dmc_wl_put(display, upper_reg);
intel_dmc_wl_put(display, lower_reg);
return val;
}
static inline void
intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
{
intel_dmc_wl_get(display, reg);
intel_uncore_posting_read(__to_uncore(display), reg);
intel_dmc_wl_put(display, reg);
}
static inline void
intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
{
intel_dmc_wl_get(display, reg);
intel_uncore_write(__to_uncore(display), reg, val);
intel_dmc_wl_put(display, reg);
}
static inline u32
__intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
u32 clear, u32 set)
{
return intel_uncore_rmw(__to_uncore(display), reg, clear, set);
}
static inline u32
intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
{
u32 val;
intel_dmc_wl_get(display, reg);
val = __intel_de_rmw_nowl(display, reg, clear, set);
intel_dmc_wl_put(display, reg);
return val;
}
static inline int
__intel_de_wait_for_register_nowl(struct intel_display *display,
i915_reg_t reg,
u32 mask, u32 value, unsigned int timeout)
{
return intel_wait_for_register(__to_uncore(display), reg, mask,
value, timeout);
}
static inline int
__intel_de_wait_for_register_atomic_nowl(struct intel_display *display,
i915_reg_t reg,
u32 mask, u32 value,
unsigned int fast_timeout_us)
{
return __intel_wait_for_register(__to_uncore(display), reg, mask,
value, fast_timeout_us, 0, NULL);
}
static inline int
intel_de_wait(struct intel_display *display, i915_reg_t reg,
u32 mask, u32 value, unsigned int timeout)
{
int ret;
intel_dmc_wl_get(display, reg);
ret = __intel_de_wait_for_register_nowl(display, reg, mask, value,
timeout);
intel_dmc_wl_put(display, reg);
return ret;
}
static inline int
intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
u32 mask, u32 value, unsigned int timeout)
{
int ret;
intel_dmc_wl_get(display, reg);
ret = intel_wait_for_register_fw(__to_uncore(display), reg, mask,
value, timeout);
intel_dmc_wl_put(display, reg);
return ret;
}
static inline int
intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
u32 mask, u32 value,
unsigned int fast_timeout_us,
unsigned int slow_timeout_ms, u32 *out_value)
{
int ret;
intel_dmc_wl_get(display, reg);
ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
value,
fast_timeout_us, slow_timeout_ms, out_value);
intel_dmc_wl_put(display, reg);
return ret;
}
static inline int
intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
u32 mask, unsigned int timeout)
{
return intel_de_wait(display, reg, mask, mask, timeout);
}
static inline int
intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg,
u32 mask, unsigned int timeout)
{
return intel_de_wait(display, reg, mask, 0, timeout);
}
/*
* Unlocked mmio-accessors, think carefully before using these.
*
* Certain architectures will die if the same cacheline is concurrently accessed
* by different clients (e.g. on Ivybridge). Access to registers should
* therefore generally be serialised, by either the dev_priv->uncore.lock or
* a more localised lock guarding all access to that bank of registers.
*/
static inline u32
intel_de_read_fw(struct intel_display *display, i915_reg_t reg)
{
u32 val;
val = intel_uncore_read_fw(__to_uncore(display), reg);
trace_i915_reg_rw(false, reg, val, sizeof(val), true);
return val;
}
static inline void
intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
{
trace_i915_reg_rw(true, reg, val, sizeof(val), true);
intel_uncore_write_fw(__to_uncore(display), reg, val);
}
static inline u32
intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
{
return intel_uncore_read_notrace(__to_uncore(display), reg);
}
static inline void
intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)
{
intel_uncore_write_notrace(__to_uncore(display), reg, val);
}
static __always_inline void
intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
i915_reg_t reg, u32 val)
{
if (dsb)
intel_dsb_reg_write(dsb, reg, val);
else
intel_de_write_fw(display, reg, val);
}
#endif /* __INTEL_DE_H__ */
|
