1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/st,stm32-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 SPI Controller
description: |
The STM32 SPI controller is used to communicate with external devices using
the Serial Peripheral Interface. It supports full-duplex, half-duplex and
simplex synchronous serial communication with external devices. It supports
from 4 to 32-bit data size.
maintainers:
- Erwan Leray <erwan.leray@foss.st.com>
- Fabrice Gasnier <fabrice.gasnier@foss.st.com>
allOf:
- $ref: spi-controller.yaml#
- if:
properties:
compatible:
contains:
const: st,stm32f4-spi
then:
properties:
st,spi-midi-ns: false
sram: false
dmas:
maxItems: 2
dma-names:
items:
- const: rx
- const: tx
- if:
properties:
compatible:
contains:
const: st,stm32mp25-spi
then:
properties:
sram: false
dmas:
maxItems: 2
dma-names:
items:
- const: rx
- const: tx
properties:
compatible:
enum:
- st,stm32f4-spi
- st,stm32f7-spi
- st,stm32h7-spi
- st,stm32mp25-spi
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
resets:
maxItems: 1
dmas:
description: |
DMA specifiers for tx and rx channels. DMA fifo mode must be used. See
the STM32 DMA bindings Documentation/devicetree/bindings/dma/stm32/st,*dma.yaml
minItems: 2
items:
- description: rx DMA channel
- description: tx DMA channel
- description: rxm2m MDMA channel
dma-names:
minItems: 2
items:
- const: rx
- const: tx
- const: rxm2m
sram:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Phandles to a reserved SRAM region which is used as temporary
storage memory between DMA and MDMA engines.
The region should be defined as child node of the AHB SRAM node
as per the generic bindings in Documentation/devicetree/bindings/sram/sram.yaml
access-controllers:
minItems: 1
maxItems: 2
required:
- compatible
- reg
- clocks
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
spi@4000b000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32h7-spi";
reg = <0x4000b000 0x400>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI2_K>;
resets = <&rcc SPI2_R>;
dmas = <&dmamux1 0 39 0x400 0x05>,
<&dmamux1 1 40 0x400 0x05>;
dma-names = "rx", "tx";
cs-gpios = <&gpioa 11 0>;
};
...
|
