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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (c) 2020 MediaTek Inc.
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
*/
#ifndef _DT_BINDINGS_POWER_MT8192_POWER_H
#define _DT_BINDINGS_POWER_MT8192_POWER_H
#define MT8192_POWER_DOMAIN_AUDIO 0
#define MT8192_POWER_DOMAIN_CONN 1
#define MT8192_POWER_DOMAIN_MFG0 2
#define MT8192_POWER_DOMAIN_MFG1 3
#define MT8192_POWER_DOMAIN_MFG2 4
#define MT8192_POWER_DOMAIN_MFG3 5
#define MT8192_POWER_DOMAIN_MFG4 6
#define MT8192_POWER_DOMAIN_MFG5 7
#define MT8192_POWER_DOMAIN_MFG6 8
#define MT8192_POWER_DOMAIN_DISP 9
#define MT8192_POWER_DOMAIN_IPE 10
#define MT8192_POWER_DOMAIN_ISP 11
#define MT8192_POWER_DOMAIN_ISP2 12
#define MT8192_POWER_DOMAIN_MDP 13
#define MT8192_POWER_DOMAIN_VENC 14
#define MT8192_POWER_DOMAIN_VDEC 15
#define MT8192_POWER_DOMAIN_VDEC2 16
#define MT8192_POWER_DOMAIN_CAM 17
#define MT8192_POWER_DOMAIN_CAM_RAWA 18
#define MT8192_POWER_DOMAIN_CAM_RAWB 19
#define MT8192_POWER_DOMAIN_CAM_RAWC 20
#endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */
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