// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

/dts-v1/;

#include <dt-bindings/usb/pd.h>
#include "imx8qm.dtsi"

/ {
	model = "Freescale i.MX8QM MEK";
	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";

	chosen {
		stdout-path = &lpuart0;
	};

	cpus {
		/delete-node/ cpu-map;
		/delete-node/ cpu@100;
		/delete-node/ cpu@101;
	};

	thermal-zones {
		/delete-node/ cpu1-thermal;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
	};

	xtal24m: clock-xtal24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "xtal_24MHz";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		vdev0vring0: memory@90000000 {
			reg = <0 0x90000000 0 0x8000>;
			no-map;
		};

		vdev0vring1: memory@90008000 {
			reg = <0 0x90008000 0 0x8000>;
			no-map;
		};

		vdev1vring0: memory@90010000 {
			reg = <0 0x90010000 0 0x8000>;
			no-map;
		};

		vdev1vring1: memory@90018000 {
			reg = <0 0x90018000 0 0x8000>;
			no-map;
		};

		rsc_table0: memory@900ff000 {
			reg = <0 0x900ff000 0 0x1000>;
			no-map;
		};

		vdev2vring0: memory@90100000 {
			reg = <0 0x90100000 0 0x8000>;
			no-map;
		};

		vdev2vring1: memory@90108000 {
			reg = <0 0x90108000 0 0x8000>;
			no-map;
		};

		vdev3vring0: memory@90110000 {
			reg = <0 0x90110000 0 0x8000>;
			no-map;
		};

		vdev3vring1: memory@90118000 {
			reg = <0 0x90118000 0 0x8000>;
			no-map;
		};

		rsc_table1: memory@901ff000 {
			reg = <0 0x901ff000 0 0x1000>;
			no-map;
		};

		vdevbuffer: memory@90400000 {
			compatible = "shared-dma-pool";
			reg = <0 0x90400000 0 0x100000>;
			no-map;
		};

		dsp_reserved: memory@92400000 {
			reg = <0 0x92400000 0 0x1000000>;
			no-map;
		};

		dsp_vdev0vring0: memory@942f0000 {
			reg = <0 0x942f0000 0 0x8000>;
			no-map;
		};

		dsp_vdev0vring1: memory@942f8000 {
			reg = <0 0x942f8000 0 0x8000>;
			no-map;
		};

		dsp_vdev0buffer: memory@94300000 {
			compatible = "shared-dma-pool";
			reg = <0 0x94300000 0 0x100000>;
			no-map;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0xc0000000 0 0x3c000000>;
			size = <0 0x3c000000>;
			linux,cma-default;
			reusable;
		};
	};

	lvds_backlight0: backlight-lvds0 {
		compatible = "pwm-backlight";
		pwms = <&qm_pwm_lvds0 0 100000 0>;
		brightness-levels = <0 100>;
		num-interpolated-steps = <100>;
		default-brightness-level = <80>;
	};

	lvds_backlight1: backlight-lvds1 {
		compatible = "pwm-backlight";
		pwms = <&pwm_lvds1 0 100000 0>;
		brightness-levels = <0 100>;
		num-interpolated-steps = <100>;
		default-brightness-level = <80>;
	};

	i2c-mux {
		compatible = "i2c-mux-gpio";
		mux-gpios = <&lsio_gpio5 3 GPIO_ACTIVE_HIGH>; /* needs to be an unused GPIO */
		i2c-parent = <&i2c1>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			wm8960: audio-codec@1a {
				compatible = "wlf,wm8960";
				reg = <0x1a>;
				clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
				clock-names = "mclk";
				assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
						  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
						  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
						  <&mclkout0_lpcg IMX_LPCG_CLK_0>;
				assigned-clock-rates = <786432000>,
						       <49152000>,
						       <12288000>,
						       <12288000>;
				wlf,shared-lrclk;
				wlf,hp-cfg = <2 2 3>;
				wlf,gpio-cfg = <1 3>;
				AVDD-supply = <&reg_audio_3v3>;
				DBVDD-supply = <&reg_audio_1v8>;
				DCVDD-supply = <&reg_audio_1v8>;
				SPKVDD1-supply = <&reg_audio_5v>;
				SPKVDD2-supply = <&reg_audio_5v>;
			};
		};

		i2c@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			wm8962: wm8962@1a {
				compatible = "wlf,wm8962";
				reg = <0x1a>;
				clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
				assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
						  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
						  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
						  <&mclkout0_lpcg IMX_LPCG_CLK_0>;
				assigned-clock-rates = <786432000>,
						       <49152000>,
						       <12288000>,
						       <12288000>;
				DCVDD-supply = <&reg_audio_1v8>;
				DBVDD-supply = <&reg_audio_1v8>;
				AVDD-supply = <&reg_audio_1v8>;
				CPVDD-supply = <&reg_audio_1v8>;
				MICVDD-supply = <&reg_audio_3v3>;
				PLLVDD-supply = <&reg_audio_1v8>;
				SPKVDD1-supply = <&reg_audio_5v>;
				SPKVDD2-supply = <&reg_audio_5v>;
			};
		};

	};

	mux-controller {
		compatible = "nxp,cbdtu02043", "gpio-sbu-mux";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_typec_mux>;
		select-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>;
		enable-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
		orientation-switch;

		port {
			usb3_data_ss: endpoint {
				remote-endpoint = <&typec_con_ss>;
			};
		};
	};

	reg_1v5: regulator-1v5 {
		compatible = "regulator-fixed";
		regulator-name = "1v5";
		regulator-min-microvolt = <1500000>;
		regulator-max-microvolt = <1500000>;
	};

	reg_1v8: regulator-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_2v8: regulator-2v8 {
		compatible = "regulator-fixed";
		regulator-name = "2v8";
		regulator-min-microvolt = <2800000>;
		regulator-max-microvolt = <2800000>;
	};

	reg_usdhc2_vmmc: usdhc2-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "SD1_SPWR";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_audio: regulator-audio {
		compatible = "regulator-fixed";
		regulator-name = "cs42888_supply";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_fec2_supply: regulator-fec2-nvcc {
		compatible = "regulator-fixed";
		regulator-name = "fec2_nvcc";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can01_en: regulator-can01-gen {
		compatible = "regulator-fixed";
		regulator-name = "can01-en";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can2_en: regulator-can2-gen {
		compatible = "regulator-fixed";
		regulator-name = "can2-en";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can01_stby: regulator-can01-stby {
		compatible = "regulator-fixed";
		regulator-name = "can01-stby";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&reg_can01_en>;
	};

	reg_can2_stby: regulator-can2-stby {
		compatible = "regulator-fixed";
		regulator-name = "can2-stby";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&reg_can2_en>;
	};

	reg_pciea: regulator-pcie {
		compatible = "regulator-fixed";
		pinctrl-0 = <&pinctrl_pciea_reg>;
		pinctrl-names = "default";
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "mpcie_3v3";
		gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_vref_1v8: regulator-adc-vref {
		compatible = "regulator-fixed";
		regulator-name = "vref_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_audio_5v: regulator-audio-pwr {
		compatible = "regulator-fixed";
		regulator-name = "audio-5v";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	reg_audio_3v3: regulator-audio-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "audio-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
	};

	reg_audio_1v8: regulator-audio-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "audio-1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		regulator-boot-on;
	};

	bt_sco_codec: audio-codec-bt {
		compatible = "linux,bt-sco";
		#sound-dai-cells = <1>;
	};

	sound-bt-sco {
		compatible = "simple-audio-card";
		simple-audio-card,name = "bt-sco-audio";
		simple-audio-card,format = "dsp_a";
		simple-audio-card,bitclock-inversion;
		simple-audio-card,frame-master = <&btcpu>;
		simple-audio-card,bitclock-master = <&btcpu>;

		btcpu: simple-audio-card,cpu {
			sound-dai = <&sai0>;
			dai-tdm-slot-num = <2>;
			dai-tdm-slot-width = <16>;
		};

		simple-audio-card,codec {
			sound-dai = <&bt_sco_codec 1>;
		};
	};

	sound-cs42888 {
		compatible = "fsl,imx-audio-cs42888";
		model = "imx-cs42888";
		audio-cpu = <&esai0>;
		audio-codec = <&cs42888>;
		audio-asrc = <&asrc0>;
		audio-routing = "Line Out Jack", "AOUT1L",
				"Line Out Jack", "AOUT1R",
				"Line Out Jack", "AOUT2L",
				"Line Out Jack", "AOUT2R",
				"Line Out Jack", "AOUT3L",
				"Line Out Jack", "AOUT3R",
				"Line Out Jack", "AOUT4L",
				"Line Out Jack", "AOUT4R",
				"AIN1L", "Line In Jack",
				"AIN1R", "Line In Jack",
				"AIN2L", "Line In Jack",
				"AIN2R", "Line In Jack";
	};

	sound-wm8960 {
		compatible = "fsl,imx-audio-wm8960";
		model = "wm8960-audio";
		audio-cpu = <&sai1>;
		audio-codec = <&wm8960>;
		hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
		audio-routing =	"Headphone Jack", "HP_L",
				"Headphone Jack", "HP_R",
				"Ext Spk", "SPK_LP",
				"Ext Spk", "SPK_LN",
				"Ext Spk", "SPK_RP",
				"Ext Spk", "SPK_RN",
				"LINPUT1", "Mic Jack",
				"Mic Jack", "MICB";
	};

	sound-wm8962 {
		compatible = "fsl,imx-audio-wm8962";
		model = "wm8962-audio";
		audio-cpu = <&sai1>;
		audio-codec = <&wm8962>;
		hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
		audio-routing = "Headphone Jack", "HPOUTL",
				"Headphone Jack", "HPOUTR",
				"Ext Spk", "SPKOUTL",
				"Ext Spk", "SPKOUTR",
				"AMIC", "MICBIAS",
				"IN1R", "AMIC",
				"IN3R", "AMIC";
	};

	imx8qm-cm4-0 {
		compatible = "fsl,imx8qm-cm4";
		clocks = <&clk_dummy>;
		mbox-names = "tx", "rx", "rxdb";
		mboxes = <&lsio_mu5 0 1
			  &lsio_mu5 1 1
			  &lsio_mu5 3 1>;
		memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
				<&vdev1vring0>, <&vdev1vring1>, <&rsc_table0>;
		power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;

		fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
		fsl,entry-address = <0x34fe0000>;
	};

	imx8qm-cm4-1 {
		compatible = "fsl,imx8qm-cm4";
		clocks = <&clk_dummy>;
		mbox-names = "tx", "rx", "rxdb";
		mboxes = <&lsio_mu6 0 1
			  &lsio_mu6 1 1
			  &lsio_mu6 3 1>;
		memory-region = <&vdevbuffer>, <&vdev2vring0>, <&vdev2vring1>,
				<&vdev3vring0>, <&vdev3vring1>, <&rsc_table1>;
		power-domains = <&pd IMX_SC_R_M4_1_PID0>, <&pd IMX_SC_R_M4_1_MU_1A>;

		fsl,resource-id = <IMX_SC_R_M4_1_PID0>;
		fsl,entry-address = <0x38fe0000>;
	};

};

&adc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc0>;
	vref-supply = <&reg_vref_1v8>;
	status = "okay";
};

&amix {
	status = "okay";
};

&asrc0 {
	fsl,asrc-rate = <48000>;
	status = "okay";
};

&cm41_i2c {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_cm41_i2c>;
	status = "okay";

	pca6416: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	cs42888: audio-codec@48 {
		compatible = "cirrus,cs42888";
		reg = <0x48>;
		clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
		clock-names = "mclk";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_cs42888_reset>;
		VA-supply = <&reg_audio>;
		VD-supply = <&reg_audio>;
		VLS-supply = <&reg_audio>;
		VLC-supply = <&reg_audio>;
		reset-gpios = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>;
		assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
				  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
				  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
				  <&mclkout0_lpcg IMX_LPCG_CLK_0>;
		assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
	};
};

&cm41_intmux {
	status = "okay";
};

&esai0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esai0>;
	assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
			  <&esai0_lpcg IMX_LPCG_CLK_4>;
	assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>;
	assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
	status = "okay";
};

&hsio_phy {
	fsl,hsio-cfg = "pciea-pcieb-sata";
	fsl,refclk-pad-mode = "input";
	status = "okay";
};

&i2c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	accelerometer@19 {
		compatible = "st,lsm303agr-accel";
		reg = <0x19>;
	};

	gyrometer@20 {
		compatible = "nxp,fxas21002c";
		reg = <0x20>;
	};

	light-sensor@44 {
		compatible = "isil,isl29023";
		reg = <0x44>;
		interrupt-parent = <&lsio_gpio4>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
	};

	pressure-sensor@60 {
		compatible = "fsl,mpl3115";
		reg = <0x60>;
	};

	max7322: gpio@68 {
		compatible = "maxim,max7322";
		reg = <0x68>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	gyrometer@69 {
		compatible = "st,l3g4200d-gyro";
		reg = <0x69>;
	};

	ptn5110: tcpc@51 {
		compatible = "nxp,ptn5110", "tcpci";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_typec>;
		reg = <0x51>;
		interrupt-parent = <&lsio_gpio4>;
		interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";

		usb_con1: connector {
			compatible = "usb-c-connector";
			label = "USB-C";
			power-role = "source";
			data-role = "dual";
			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					typec_dr_sw: endpoint {
						remote-endpoint = <&usb3_drd_sw>;
					};
				};

				port@1 {
					reg = <1>;
					typec_con_ss: endpoint {
						remote-endpoint = <&usb3_data_ss>;
					};
				};
			};
		};
	};
};

&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&i2c1_lvds0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
	clock-frequency = <100000>;
	status = "okay";
};

&i2c1_lvds1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
	clock-frequency = <100000>;
	status = "okay";
};

&i2c0_mipi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mipi0_lpi2c0>;
	clock-frequency = <100000>;
	status = "okay";
};

&i2c0_mipi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mipi1_lpi2c0>;
	clock-frequency = <100000>;
	status = "okay";
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can01_stby>;
	status = "okay";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can01_stby>;
	status = "okay";
};

&flexcan3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan3>;
	xceiver-supply = <&reg_can2_stby>;
	status = "okay";
};

&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&lpuart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart2>;
	status = "okay";
};

&lpuart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart3>;
	status = "okay";
};

&lpspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
	cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&lsio_mu5 {
	status = "okay";
};

&lsio_mu6 {
	status = "okay";
};

&flexspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	flash0: flash@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <133000000>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec2>;
	phy-mode = "rgmii-txid";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_fec2_supply>;
	nvmem-cells = <&fec_mac1>;
	nvmem-cell-names = "mac-address";
	rx-internal-delay-ps = <2000>;
	fsl,magic-packet;
	status = "okay";
};

&pciea {
	phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
	phy-names = "pcie-phy";
	pinctrl-0 = <&pinctrl_pciea>;
	pinctrl-names = "default";
	reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
	vpcie-supply = <&reg_pciea>;
	status = "okay";
};

&pcieb {
	phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;
	phy-names = "pcie-phy";
	pinctrl-0 = <&pinctrl_pcieb>;
	pinctrl-names = "default";
	reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
	status = "disabled";
};

&qm_pwm_lvds0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_lvds0>;
	status = "okay";
};

&pwm_lvds1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_lvds1>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&usb3_phy {
	status = "okay";
};

&usbotg3 {
	status = "okay";
};

&usbotg3_cdns3 {
	dr_mode = "otg";
	usb-role-switch;
	status = "okay";

	port {
		usb3_drd_sw: endpoint {
			remote-endpoint = <&typec_dr_sw>;
		};
	};
};

&sai0 {
	#sound-dai-cells = <0>;
	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
			  <&sai0_lpcg IMX_LPCG_CLK_4>;
	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai0>;
	status = "okay";
};

&sai1 {
	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
			  <&sai1_lpcg IMX_LPCG_CLK_4>;
	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "okay";
};

&sai6 {
	assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
			  <&sai6_lpcg IMX_LPCG_CLK_4>;
	assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
	assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
	fsl,sai-asynchronous;
	status = "okay";
};

&sai7 {
	assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
			  <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
			  <&sai7_lpcg IMX_LPCG_CLK_4>;
	assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
	assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
	fsl,sai-asynchronous;
	status = "okay";
};

&sata {
	status = "okay";
};

&vpu_dsp {
	memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
			<&dsp_vdev0vring1>, <&dsp_reserved>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0			0x0600004c
			IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31			0x0600004c
		>;
	};

	pinctrl_cs42888_reset: cs42888_resetgrp {
		fsl,pins = <
			IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25			0x0600004c
		>;
	};

	pinctrl_i2c_mipi_csi0: i2c-mipi-csi0grp {
		fsl,pins = <
			IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL		0xc2000020
			IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA		0xc2000020
		>;
	};

	pinctrl_i2c_mipi_csi1: i2c-mipi-csi1grp {
		fsl,pins = <
			IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL		0xc2000020
			IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA		0xc2000020
		>;
	};

	pinctrl_i2c0: i2c0grp {
		fsl,pins = <
			IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL			0x06000021
			IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA			0x06000021
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c
			IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c
		>;
	};

	pinctrl_i2c1_gpio: i2c1gpio-grp {
		fsl,pins = <
			IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14		0xc600004c
			IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15	0xc600004c
		>;
	};

	pinctrl_adc0: adc0grp {
		fsl,pins = <
			IMX8QM_ADC_IN0_DMA_ADC0_IN0				0xc0000060
		>;
	};

	pinctrl_cm41_i2c: cm41i2cgrp {
		fsl,pins = <
			IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA			0x0600004c
			IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL			0x0600004c
		>;
	};

	pinctrl_esai0: esai0grp {
		fsl,pins = <
			IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR				0xc6000040
			IMX8QM_ESAI0_FST_AUD_ESAI0_FST				0xc6000040
			IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR			0xc6000040
			IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT			0xc6000040
			IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0				0xc6000040
			IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1				0xc6000040
			IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3			0xc6000040
			IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2			0xc6000040
			IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1			0xc6000040
			IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0			0xc6000040
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020
			IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
			IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
			IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
			IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
			IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
			IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
			IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
			IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
			IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
			IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
			IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
			IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
			IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
		>;
	};

	pinctrl_lpspi2: lpspi2grp {
		fsl,pins = <
			IMX8QM_SPI2_SCK_DMA_SPI2_SCK		0x06000040
			IMX8QM_SPI2_SDO_DMA_SPI2_SDO		0x06000040
			IMX8QM_SPI2_SDI_DMA_SPI2_SDI		0x06000040
		>;
	};

	pinctrl_lpspi2_cs: lpspi2csgrp {
		fsl,pins = <
			IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10		0x21
		>;
	};

	pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp {
		fsl,pins = <
			IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL      0xc6000020
			IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA      0xc6000020
			IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19         0x00000020
		>;
	};

	pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp {
		fsl,pins = <
			IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL      0xc6000020
			IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA      0xc6000020
			IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23         0x00000020
		>;
	};

	pinctrl_flexspi0: flexspi0grp {
		fsl,pins = <
			IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x06000021
			IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1     0x06000021
			IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2     0x06000021
			IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3     0x06000021
			IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS         0x06000021
			IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B     0x06000021
			IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B     0x06000021
			IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK       0x06000021
			IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK       0x06000021
			IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0     0x06000021
			IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1     0x06000021
			IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2     0x06000021
			IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3     0x06000021
			IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS         0x06000021
			IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B     0x06000021
			IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B     0x06000021
		>;
	};

	pinctrl_fec2: fec2grp {
		fsl,pins = <
			IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD		0x000014a0
			IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060
			IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC		0x00000060
			IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0		0x00000060
			IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1		0x00000060
			IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2		0x00000060
			IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3		0x00000060
			IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC		0x00000060
			IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060
			IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0		0x00000060
			IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1		0x00000060
			IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2		0x00000060
			IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3		0x00000060
		>;
	};

	pinctrl_flexcan1: flexcan0grp {
		fsl,pins = <
			IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX			0x21
			IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX			0x21
		>;
	};

	pinctrl_flexcan2: flexcan1grp {
		fsl,pins = <
			IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX			0x21
			IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX			0x21
		>;
	};

	pinctrl_flexcan3: flexcan3grp {
		fsl,pins = <
			IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX			0x21
			IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX			0x21
		>;
	};

	pinctrl_lpuart0: lpuart0grp {
		fsl,pins = <
			IMX8QM_UART0_RX_DMA_UART0_RX				0x06000020
			IMX8QM_UART0_TX_DMA_UART0_TX				0x06000020
		>;
	};

	pinctrl_lpuart2: lpuart2grp {
		fsl,pins = <
			IMX8QM_UART0_RTS_B_DMA_UART2_RX				0x06000020
			IMX8QM_UART0_CTS_B_DMA_UART2_TX				0x06000020
		>;
	};

	pinctrl_lpuart3: lpuart3grp {
		fsl,pins = <
			IMX8QM_M41_GPIO0_00_DMA_UART3_RX			0x06000020
			IMX8QM_M41_GPIO0_01_DMA_UART3_TX			0x06000020
		>;
	};

	pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
		fsl,pins = <
			IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL	0xc600004c
			IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA	0xc600004c
		>;
	};

	pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
		fsl,pins = <
			IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL	0xc600004c
			IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA	0xc600004c
		>;
	};

	pinctrl_mipi_csi0: mipi-csi0grp {
		fsl,pins = <
			IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27		0xC0000041
			IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28		0xC0000041
			IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT	0xC0000041
		>;
	};

	pinctrl_mipi_csi1: mipi-csi1grp {
		fsl,pins = <
			IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30		0xC0000041
			IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31		0xC0000041
			IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT	0xC0000041
		>;
	};

	pinctrl_pciea: pcieagrp {
		fsl,pins = <
			IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28		0x04000021
			IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29		0x06000021
			IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x20
		>;
	};

	pinctrl_pciea_reg: pcieareggrp {
		fsl,pins = <
			IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13			0x06000021
		>;
	};

	pinctrl_pcieb: pciebgrp {
		fsl,pins = <
			IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B		0x06000021
			IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31		0x04000021
			IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00		0x06000021
		>;
	};

	pinctrl_pwm_lvds0: pwmlvds0grp {
		fsl,pins = <
			IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT		0x00000020
		>;
	};

	pinctrl_pwm_lvds1: pwmlvds1grp {
		fsl,pins = <
			IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT		0x00000020
		>;
	};

	pinctrl_sai0: sai0grp {
		fsl,pins = <
			IMX8QM_SPI0_CS1_AUD_SAI0_TXC				0x0600004c
			IMX8QM_SPI2_CS1_AUD_SAI0_TXFS				0x0600004c
			IMX8QM_SAI1_RXFS_AUD_SAI0_RXD				0x0600004c
			IMX8QM_SAI1_RXC_AUD_SAI0_TXD				0x0600006c
		>;
	};

	pinctrl_sai1: sai1grp {
		fsl,pins = <
			IMX8QM_SAI1_RXD_AUD_SAI1_RXD				0x06000040
			IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS				0x06000040
			IMX8QM_SAI1_TXD_AUD_SAI1_TXD				0x06000060
			IMX8QM_SAI1_TXC_AUD_SAI1_TXC				0x06000040
		>;
	};

	pinctrl_typec: typecgrp {
		fsl,pins = <
			IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26		0x00000021
		>;
	};

	pinctrl_typec_mux: typecmuxgrp {
		fsl,pins = <
			IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19		0x60
			IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06		0x60
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK				0x06000041
			IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD				0x00000021
			IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
			IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
			IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
			IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
			IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
			IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
			IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
			IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
			IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
			IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
			IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
			IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
			IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
			IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
			IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
		>;
	};
};