1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
|
//===- SystemZInstrFP.td - SystemZ FP Instruction defs --------*- tblgen-*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the SystemZ (binary) floating point instructions in
// TableGen format.
//
//===----------------------------------------------------------------------===//
// FIXME: multiclassify!
//===----------------------------------------------------------------------===//
// FP Pattern fragments
def fpimm0 : PatLeaf<(fpimm), [{
return N->isExactlyValue(+0.0);
}]>;
def fpimmneg0 : PatLeaf<(fpimm), [{
return N->isExactlyValue(-0.0);
}]>;
let Uses = [PSW], usesCustomInserter = 1 in {
def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
"# SelectF32 PSEUDO",
[(set FP32:$dst,
(SystemZselect FP32:$src1, FP32:$src2, imm:$cc, PSW))]>;
def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
"# SelectF64 PSEUDO",
[(set FP64:$dst,
(SystemZselect FP64:$src1, FP64:$src2, imm:$cc, PSW))]>;
}
//===----------------------------------------------------------------------===//
// Move Instructions
// Floating point constant loads.
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def LD_Fp032 : Pseudo<(outs FP32:$dst), (ins),
"lzer\t{$dst}",
[(set FP32:$dst, fpimm0)]>;
def LD_Fp064 : Pseudo<(outs FP64:$dst), (ins),
"lzdr\t{$dst}",
[(set FP64:$dst, fpimm0)]>;
}
let neverHasSideEffects = 1 in {
def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
"ler\t{$dst, $src}",
[]>;
def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
"ldr\t{$dst, $src}",
[]>;
}
let canFoldAsLoad = 1, isReMaterializable = 1 in {
def FMOV32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
"le\t{$dst, $src}",
[(set FP32:$dst, (load rriaddr12:$src))]>;
def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
"ley\t{$dst, $src}",
[(set FP32:$dst, (load rriaddr:$src))]>;
def FMOV64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
"ld\t{$dst, $src}",
[(set FP64:$dst, (load rriaddr12:$src))]>;
def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
"ldy\t{$dst, $src}",
[(set FP64:$dst, (load rriaddr:$src))]>;
}
def FMOV32mr : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src),
"ste\t{$src, $dst}",
[(store FP32:$src, rriaddr12:$dst)]>;
def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src),
"stey\t{$src, $dst}",
[(store FP32:$src, rriaddr:$dst)]>;
def FMOV64mr : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src),
"std\t{$src, $dst}",
[(store FP64:$src, rriaddr12:$dst)]>;
def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src),
"stdy\t{$src, $dst}",
[(store FP64:$src, rriaddr:$dst)]>;
def FCOPYSIGN32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
"cpsdr\t{$dst, $src2, $src1}",
[(set FP32:$dst, (fcopysign FP32:$src1, FP32:$src2))]>;
def FCOPYSIGN64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
"cpsdr\t{$dst, $src2, $src1}",
[(set FP64:$dst, (fcopysign FP64:$src1, FP64:$src2))]>;
//===----------------------------------------------------------------------===//
// Arithmetic Instructions
let Defs = [PSW] in {
def FNEG32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
"lcebr\t{$dst, $src}",
[(set FP32:$dst, (fneg FP32:$src)),
(implicit PSW)]>;
def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
"lcdbr\t{$dst, $src}",
[(set FP64:$dst, (fneg FP64:$src)),
(implicit PSW)]>;
def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
"lpebr\t{$dst, $src}",
[(set FP32:$dst, (fabs FP32:$src)),
(implicit PSW)]>;
def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
"lpdbr\t{$dst, $src}",
[(set FP64:$dst, (fabs FP64:$src)),
(implicit PSW)]>;
def FNABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
"lnebr\t{$dst, $src}",
[(set FP32:$dst, (fneg(fabs FP32:$src))),
(implicit PSW)]>;
def FNABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
"lndbr\t{$dst, $src}",
[(set FP64:$dst, (fneg(fabs FP64:$src))),
(implicit PSW)]>;
}
let Constraints = "$src1 = $dst" in {
let Defs = [PSW] in {
let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
"aebr\t{$dst, $src2}",
[(set FP32:$dst, (fadd FP32:$src1, FP32:$src2)),
(implicit PSW)]>;
def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
"adbr\t{$dst, $src2}",
[(set FP64:$dst, (fadd FP64:$src1, FP64:$src2)),
(implicit PSW)]>;
}
def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
"aeb\t{$dst, $src2}",
[(set FP32:$dst, (fadd FP32:$src1, (load rriaddr12:$src2))),
(implicit PSW)]>;
def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
"adb\t{$dst, $src2}",
[(set FP64:$dst, (fadd FP64:$src1, (load rriaddr12:$src2))),
(implicit PSW)]>;
def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
"sebr\t{$dst, $src2}",
[(set FP32:$dst, (fsub FP32:$src1, FP32:$src2)),
(implicit PSW)]>;
def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
"sdbr\t{$dst, $src2}",
[(set FP64:$dst, (fsub FP64:$src1, FP64:$src2)),
(implicit PSW)]>;
def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
"seb\t{$dst, $src2}",
[(set FP32:$dst, (fsub FP32:$src1, (load rriaddr12:$src2))),
(implicit PSW)]>;
def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
"sdb\t{$dst, $src2}",
[(set FP64:$dst, (fsub FP64:$src1, (load rriaddr12:$src2))),
(implicit PSW)]>;
} // Defs = [PSW]
let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
"meebr\t{$dst, $src2}",
[(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>;
def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
"mdbr\t{$dst, $src2}",
[(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>;
}
def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
"meeb\t{$dst, $src2}",
[(set FP32:$dst, (fmul FP32:$src1, (load rriaddr12:$src2)))]>;
def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
"mdb\t{$dst, $src2}",
[(set FP64:$dst, (fmul FP64:$src1, (load rriaddr12:$src2)))]>;
def FMADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
"maebr\t{$dst, $src3, $src2}",
[(set FP32:$dst, (fadd (fmul FP32:$src2, FP32:$src3),
FP32:$src1))]>;
def FMADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2, FP32:$src3),
"maeb\t{$dst, $src3, $src2}",
[(set FP32:$dst, (fadd (fmul (load rriaddr12:$src2),
FP32:$src3),
FP32:$src1))]>;
def FMADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
"madbr\t{$dst, $src3, $src2}",
[(set FP64:$dst, (fadd (fmul FP64:$src2, FP64:$src3),
FP64:$src1))]>;
def FMADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2, FP64:$src3),
"madb\t{$dst, $src3, $src2}",
[(set FP64:$dst, (fadd (fmul (load rriaddr12:$src2),
FP64:$src3),
FP64:$src1))]>;
def FMSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
"msebr\t{$dst, $src3, $src2}",
[(set FP32:$dst, (fsub (fmul FP32:$src2, FP32:$src3),
FP32:$src1))]>;
def FMSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2, FP32:$src3),
"mseb\t{$dst, $src3, $src2}",
[(set FP32:$dst, (fsub (fmul (load rriaddr12:$src2),
FP32:$src3),
FP32:$src1))]>;
def FMSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
"msdbr\t{$dst, $src3, $src2}",
[(set FP64:$dst, (fsub (fmul FP64:$src2, FP64:$src3),
FP64:$src1))]>;
def FMSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2, FP64:$src3),
"msdb\t{$dst, $src3, $src2}",
[(set FP64:$dst, (fsub (fmul (load rriaddr12:$src2),
FP64:$src3),
FP64:$src1))]>;
def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
"debr\t{$dst, $src2}",
[(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>;
def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
"ddbr\t{$dst, $src2}",
[(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>;
def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
"deb\t{$dst, $src2}",
[(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr12:$src2)))]>;
def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
"ddb\t{$dst, $src2}",
[(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr12:$src2)))]>;
} // Constraints = "$src1 = $dst"
def FSQRT32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
"sqebr\t{$dst, $src}",
[(set FP32:$dst, (fsqrt FP32:$src))]>;
def FSQRT64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
"sqdbr\t{$dst, $src}",
[(set FP64:$dst, (fsqrt FP64:$src))]>;
def FSQRT32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
"sqeb\t{$dst, $src}",
[(set FP32:$dst, (fsqrt (load rriaddr12:$src)))]>;
def FSQRT64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
"sqdb\t{$dst, $src}",
[(set FP64:$dst, (fsqrt (load rriaddr12:$src)))]>;
def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
"ledbr\t{$dst, $src}",
[(set FP32:$dst, (fround FP64:$src))]>;
def FEXT32r64 : Pseudo<(outs FP64:$dst), (ins FP32:$src),
"ldebr\t{$dst, $src}",
[(set FP64:$dst, (fextend FP32:$src))]>;
def FEXT32m64 : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
"ldeb\t{$dst, $src}",
[(set FP64:$dst, (fextend (load rriaddr12:$src)))]>;
let Defs = [PSW] in {
def FCONVFP32 : Pseudo<(outs FP32:$dst), (ins GR32:$src),
"cefbr\t{$dst, $src}",
[(set FP32:$dst, (sint_to_fp GR32:$src)),
(implicit PSW)]>;
def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src),
"cegbr\t{$dst, $src}",
[(set FP32:$dst, (sint_to_fp GR64:$src)),
(implicit PSW)]>;
def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src),
"cdfbr\t{$dst, $src}",
[(set FP64:$dst, (sint_to_fp GR32:$src)),
(implicit PSW)]>;
def FCONVFP64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
"cdgbr\t{$dst, $src}",
[(set FP64:$dst, (sint_to_fp GR64:$src)),
(implicit PSW)]>;
def FCONVGR32 : Pseudo<(outs GR32:$dst), (ins FP32:$src),
"cfebr\t{$dst, 5, $src}",
[(set GR32:$dst, (fp_to_sint FP32:$src)),
(implicit PSW)]>;
def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
"cfdbr\t{$dst, 5, $src}",
[(set GR32:$dst, (fp_to_sint FP64:$src)),
(implicit PSW)]>;
def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
"cgebr\t{$dst, 5, $src}",
[(set GR64:$dst, (fp_to_sint FP32:$src)),
(implicit PSW)]>;
def FCONVGR64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
"cgdbr\t{$dst, 5, $src}",
[(set GR64:$dst, (fp_to_sint FP64:$src)),
(implicit PSW)]>;
} // Defs = [PSW]
def FBCONVG64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
"lgdr\t{$dst, $src}",
[(set GR64:$dst, (bitconvert FP64:$src))]>;
def FBCONVF64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
"ldgr\t{$dst, $src}",
[(set FP64:$dst, (bitconvert GR64:$src))]>;
//===----------------------------------------------------------------------===//
// Test instructions (like AND but do not produce any result)
// Integer comparisons
let Defs = [PSW] in {
def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2),
"cebr\t$src1, $src2",
[(set PSW, (SystemZcmp FP32:$src1, FP32:$src2))]>;
def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2),
"cdbr\t$src1, $src2",
[(set PSW, (SystemZcmp FP64:$src1, FP64:$src2))]>;
def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr12:$src2),
"ceb\t$src1, $src2",
[(set PSW, (SystemZcmp FP32:$src1,
(load rriaddr12:$src2)))]>;
def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr12:$src2),
"cdb\t$src1, $src2",
[(set PSW, (SystemZcmp FP64:$src1,
(load rriaddr12:$src2)))]>;
} // Defs = [PSW]
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
// Floating point constant -0.0
def : Pat<(f32 fpimmneg0), (FNEG32rr (LD_Fp032))>;
def : Pat<(f64 fpimmneg0), (FNEG64rr (LD_Fp064))>;
|
