1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
|
; RUN: llvm-as < %s | llc -march=xcore | FileCheck %s
; Only needs one ladd
define i64 @f1(i32 %x, i32 %y) nounwind {
entry:
%0 = zext i32 %x to i64 ; <i64> [#uses=1]
%1 = zext i32 %y to i64 ; <i64> [#uses=1]
%2 = add i64 %1, %0 ; <i64> [#uses=1]
ret i64 %2
}
; CHECK: f1:
; CHECK: ldc r2, 0
; CHECK-NEXT: ladd r1, r0, r1, r0, r2
; CHECK-NEXT: retsp 0
; Only needs one lsub and one neg
define i64 @f2(i32 %x, i32 %y) nounwind {
entry:
%0 = zext i32 %x to i64 ; <i64> [#uses=1]
%1 = zext i32 %y to i64 ; <i64> [#uses=1]
%2 = sub i64 %1, %0 ; <i64> [#uses=1]
ret i64 %2
}
; CHECK: f2:
; CHECK: ldc r2, 0
; CHECK-NEXT: lsub r1, r0, r1, r0, r2
; CHECK-NEXT: neg r1, r1
; CHECK-NEXT: retsp 0
; Should compile to one ladd and one add
define i64 @f3(i64 %x, i32 %y) nounwind {
entry:
%0 = zext i32 %y to i64 ; <i64> [#uses=1]
%1 = add i64 %x, %0 ; <i64> [#uses=1]
ret i64 %1
}
; CHECK: f3:
; CHECK: ldc r3, 0
; CHECK-NEXT: ladd r2, r0, r0, r2, r3
; CHECK-NEXT: add r1, r1, r2
; CHECK-NEXT: retsp 0
; Should compile to one ladd and one add
define i64 @f4(i32 %x, i64 %y) nounwind {
entry:
%0 = zext i32 %x to i64 ; <i64> [#uses=1]
%1 = add i64 %0, %y ; <i64> [#uses=1]
ret i64 %1
}
; CHECK: f4:
; CHECK: ldc r3, 0
; CHECK-NEXT: ladd r1, r0, r0, r1, r3
; CHECK-NEXT: add r1, r2, r1
; CHECK-NEXT: retsp 0
; Should compile to one lsub and one sub
define i64 @f5(i64 %x, i32 %y) nounwind {
entry:
%0 = zext i32 %y to i64 ; <i64> [#uses=1]
%1 = sub i64 %x, %0 ; <i64> [#uses=1]
ret i64 %1
}
; CHECK: f5:
; CHECK: ldc r3, 0
; CHECK-NEXT: lsub r2, r0, r0, r2, r3
; CHECK-NEXT: sub r1, r1, r2
; CHECK-NEXT: retsp 0
|
