1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
|
//===- VETargetTransformInfo.h - VE specific TTI ------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
/// \file
/// This file a TargetTransformInfo::Concept conforming object specific to the
/// VE target machine. It uses the target's detailed information to
/// provide more precise answers to certain TTI queries, while letting the
/// target independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
#define LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
#include "VE.h"
#include "VETargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
namespace llvm {
class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
using BaseT = BasicTTIImplBase<VETTIImpl>;
friend BaseT;
const VESubtarget *ST;
const VETargetLowering *TLI;
const VESubtarget *getST() const { return ST; }
const VETargetLowering *getTLI() const { return TLI; }
public:
explicit VETTIImpl(const VETargetMachine *TM, const Function &F)
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}
unsigned getNumberOfRegisters(unsigned ClassID) const { return 64; }
unsigned getRegisterBitWidth(bool Vector) const { return 64; }
unsigned getMinVectorRegisterBitWidth() const { return 64; }
};
} // namespace llvm
#endif // LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
|
