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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Test G_EXT selection using AArch64ext patterns.
...
---
name: v8s8_EXTv8i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: v8s8_EXTv8i8
; CHECK: liveins: $d0, $d1
; CHECK: %v1:fpr64 = COPY $d0
; CHECK: %v2:fpr64 = COPY $d1
; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 3
%v1:fpr(<8 x s8>) = COPY $d0
%v2:fpr(<8 x s8>) = COPY $d1
%3:gpr(s32) = G_CONSTANT i32 3
%shuf:fpr(<8 x s8>) = G_EXT %v1, %v2, %3(s32)
...
---
name: v16s8_EXTv16i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: v16s8_EXTv16i8
; CHECK: liveins: $q0, $q1
; CHECK: %v1:fpr128 = COPY $q0
; CHECK: %v2:fpr128 = COPY $q1
; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 3
%v1:fpr(<16 x s8>) = COPY $q0
%v2:fpr(<16 x s8>) = COPY $q1
%3:gpr(s32) = G_CONSTANT i32 3
%shuf:fpr(<16 x s8>) = G_EXT %v1, %v2, %3(s32)
...
---
name: v4s16_EXTv8i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: v4s16_EXTv8i8
; CHECK: liveins: $d0, $d1
; CHECK: %v1:fpr64 = COPY $d0
; CHECK: %v2:fpr64 = COPY $d1
; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 6
%v1:fpr(<4 x s16>) = COPY $d0
%v2:fpr(<4 x s16>) = COPY $d1
%3:gpr(s32) = G_CONSTANT i32 6
%shuf:fpr(<4 x s16>) = G_EXT %v1, %v2, %3(s32)
...
---
name: v8s16_EXTv16i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: v8s16_EXTv16i8
; CHECK: liveins: $q0, $q1
; CHECK: %v1:fpr128 = COPY $q0
; CHECK: %v2:fpr128 = COPY $q1
; CHECK: %shuf:fpr128 = EXTv16i8 %v2, %v1, 10
%v1:fpr(<8 x s16>) = COPY $q0
%v2:fpr(<8 x s16>) = COPY $q1
%3:gpr(s32) = G_CONSTANT i32 10
%shuf:fpr(<8 x s16>) = G_EXT %v2, %v1, %3(s32)
...
...
---
name: v4s32_EXTv16i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: v4s32_EXTv16i8
; CHECK: liveins: $q0, $q1
; CHECK: %v1:fpr128 = COPY $q0
; CHECK: %v2:fpr128 = COPY $q1
; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 12
%v1:fpr(<4 x s32>) = COPY $q0
%v2:fpr(<4 x s32>) = COPY $q1
%3:gpr(s32) = G_CONSTANT i32 12
%shuf:fpr(<4 x s32>) = G_EXT %v1, %v2, %3(s32)
...
---
name: v2s32_EXTv8i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: v2s32_EXTv8i8
; CHECK: liveins: $d0, $d1
; CHECK: %v1:fpr64 = COPY $d0
; CHECK: %v2:fpr64 = COPY $d1
; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 2
%v1:fpr(<2 x s32>) = COPY $d0
%v2:fpr(<2 x s32>) = COPY $d1
%3:gpr(s32) = G_CONSTANT i32 2
%shuf:fpr(<2 x s32>) = G_EXT %v1, %v2, %3(s32)
...
---
name: v2s64_EXTv16i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: v2s64_EXTv16i8
; CHECK: liveins: $q0, $q1
; CHECK: %v1:fpr128 = COPY $q0
; CHECK: %v2:fpr128 = COPY $q1
; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 2
%v1:fpr(<2 x s64>) = COPY $q0
%v2:fpr(<2 x s64>) = COPY $q1
%3:gpr(s32) = G_CONSTANT i32 2
%shuf:fpr(<2 x s64>) = G_EXT %v1, %v2, %3(s32)
...
|
