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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: select_f32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $s0, $s1, $w0
; CHECK-LABEL: name: select_f32
; CHECK: liveins: $s0, $s1, $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]]
; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]]
; CHECK: $wzr = ANDSWri [[COPY4]], 0, implicit-def $nzcv
; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
; CHECK: $s0 = COPY [[FCSELSrrr]]
; CHECK: RET_ReallyLR implicit $s0
%3:gpr(s32) = COPY $w0
%0:gpr(s1) = G_TRUNC %3(s32)
%1:fpr(s32) = COPY $s0
%2:fpr(s32) = COPY $s1
%5:fpr(s1) = COPY %0(s1)
%4:fpr(s32) = G_SELECT %5(s1), %1, %2
$s0 = COPY %4(s32)
RET_ReallyLR implicit $s0
...
---
name: select_f64
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0, $d1, $w0
; CHECK-LABEL: name: select_f64
; CHECK: liveins: $d0, $d1, $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]]
; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]]
; CHECK: $wzr = ANDSWri [[COPY4]], 0, implicit-def $nzcv
; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
; CHECK: $d0 = COPY [[FCSELDrrr]]
; CHECK: RET_ReallyLR implicit $d0
%3:gpr(s32) = COPY $w0
%0:gpr(s1) = G_TRUNC %3(s32)
%1:fpr(s64) = COPY $d0
%2:fpr(s64) = COPY $d1
%5:fpr(s1) = COPY %0(s1)
%4:fpr(s64) = G_SELECT %5(s1), %1, %2
$d0 = COPY %4(s64)
RET_ReallyLR implicit $d0
|
