1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
|
; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX600 %s
; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX700 %s
; RUN: llc -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX801 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX900 %s
; GCN-LABEL: {{^}}scalar_nand_i32_one_use
; GCN: s_nand_b32
define amdgpu_kernel void @scalar_nand_i32_one_use(
i32 addrspace(1)* %r0, i32 %a, i32 %b) {
entry:
%and = and i32 %a, %b
%r0.val = xor i32 %and, -1
store i32 %r0.val, i32 addrspace(1)* %r0
ret void
}
; GCN-LABEL: {{^}}scalar_nand_i32_mul_use
; GCN-NOT: s_nand_b32
; GCN: s_and_b32
; GCN: s_not_b32
; GCN: s_add_i32
define amdgpu_kernel void @scalar_nand_i32_mul_use(
i32 addrspace(1)* %r0, i32 addrspace(1)* %r1, i32 %a, i32 %b) {
entry:
%and = and i32 %a, %b
%r0.val = xor i32 %and, -1
%r1.val = add i32 %and, %a
store i32 %r0.val, i32 addrspace(1)* %r0
store i32 %r1.val, i32 addrspace(1)* %r1
ret void
}
; GCN-LABEL: {{^}}scalar_nand_i64_one_use
; GCN: s_nand_b64
define amdgpu_kernel void @scalar_nand_i64_one_use(
i64 addrspace(1)* %r0, i64 %a, i64 %b) {
entry:
%and = and i64 %a, %b
%r0.val = xor i64 %and, -1
store i64 %r0.val, i64 addrspace(1)* %r0
ret void
}
; GCN-LABEL: {{^}}scalar_nand_i64_mul_use
; GCN-NOT: s_nand_b64
; GCN: s_and_b64
; GCN: s_not_b64
; GCN: s_add_u32
; GCN: s_addc_u32
define amdgpu_kernel void @scalar_nand_i64_mul_use(
i64 addrspace(1)* %r0, i64 addrspace(1)* %r1, i64 %a, i64 %b) {
entry:
%and = and i64 %a, %b
%r0.val = xor i64 %and, -1
%r1.val = add i64 %and, %a
store i64 %r0.val, i64 addrspace(1)* %r0
store i64 %r1.val, i64 addrspace(1)* %r1
ret void
}
; GCN-LABEL: {{^}}vector_nand_i32_one_use
; GCN-NOT: s_nand_b32
; GCN: v_and_b32
; GCN: v_not_b32
define i32 @vector_nand_i32_one_use(i32 %a, i32 %b) {
entry:
%and = and i32 %a, %b
%r = xor i32 %and, -1
ret i32 %r
}
; GCN-LABEL: {{^}}vector_nand_i64_one_use
; GCN-NOT: s_nand_b64
; GCN: v_and_b32
; GCN: v_and_b32
; GCN: v_not_b32
; GCN: v_not_b32
define i64 @vector_nand_i64_one_use(i64 %a, i64 %b) {
entry:
%and = and i64 %a, %b
%r = xor i64 %and, -1
ret i64 %r
}
|
