1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512F
--- |
define <16 x i32> @test_load_v16i32_noalign(<16 x i32>* %p1) {
%r = load <16 x i32>, <16 x i32>* %p1, align 1
ret <16 x i32> %r
}
define <16 x i32> @test_load_v16i32_align(<16 x i32>* %p1) {
%r = load <16 x i32>, <16 x i32>* %p1, align 32
ret <16 x i32> %r
}
define void @test_store_v16i32_noalign(<16 x i32> %val, <16 x i32>* %p1) {
store <16 x i32> %val, <16 x i32>* %p1, align 1
ret void
}
define void @test_store_v16i32_align(<16 x i32> %val, <16 x i32>* %p1) {
store <16 x i32> %val, <16 x i32>* %p1, align 32
ret void
}
...
---
name: test_load_v16i32_noalign
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
body: |
bb.1 (%ir-block.0):
liveins: $rdi
; AVX512F-LABEL: name: test_load_v16i32_noalign
; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, $noreg, 0, $noreg :: (load 64 from %ir.p1, align 1)
; AVX512F: $zmm0 = COPY [[VMOVUPSZrm]]
; AVX512F: RET 0, implicit $zmm0
%0(p0) = COPY $rdi
%1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1)
$zmm0 = COPY %1(<16 x s32>)
RET 0, implicit $zmm0
...
---
name: test_load_v16i32_align
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
body: |
bb.1 (%ir-block.0):
liveins: $rdi
; AVX512F-LABEL: name: test_load_v16i32_align
; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, $noreg, 0, $noreg :: (load 64 from %ir.p1, align 32)
; AVX512F: $zmm0 = COPY [[VMOVUPSZrm]]
; AVX512F: RET 0, implicit $zmm0
%0(p0) = COPY $rdi
%1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 32)
$zmm0 = COPY %1(<16 x s32>)
RET 0, implicit $zmm0
...
---
name: test_store_v16i32_noalign
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
body: |
bb.1 (%ir-block.0):
liveins: $rdi, $zmm0
; AVX512F-LABEL: name: test_store_v16i32_noalign
; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
; AVX512F: VMOVUPSZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 64 into %ir.p1, align 1)
; AVX512F: RET 0
%0(<16 x s32>) = COPY $zmm0
%1(p0) = COPY $rdi
G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1)
RET 0
...
---
name: test_store_v16i32_align
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
body: |
bb.1 (%ir-block.0):
liveins: $rdi, $zmm0
; AVX512F-LABEL: name: test_store_v16i32_align
; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
; AVX512F: VMOVUPSZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store 64 into %ir.p1, align 32)
; AVX512F: RET 0
%0(<16 x s32>) = COPY $zmm0
%1(p0) = COPY $rdi
G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 32)
RET 0
...
|
