File: vect-vd0.ll

package info (click to toggle)
llvm-toolchain-13 1%3A13.0.1-11
  • links: PTS, VCS
  • area: main
  • in suites: bookworm
  • size: 1,418,840 kB
  • sloc: cpp: 5,290,826; ansic: 996,570; asm: 544,593; python: 188,212; objc: 72,027; lisp: 30,291; f90: 25,395; sh: 24,898; javascript: 9,780; pascal: 9,398; perl: 7,484; ml: 5,432; awk: 3,523; makefile: 2,913; xml: 953; cs: 573; fortran: 539
file content (22 lines) | stat: -rw-r--r-- 691 bytes parent folder | download | duplicates (14) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
 
; RUN: llc -march=hexagon < %s | FileCheck %s

; Verify __builtin_HEXAGON_V6_vd0 maps to vxor
; CHECK: v{{[0-9]*}} = vxor(v{{[0-9]*}},v{{[0-9]*}})

@g0 = common global <16 x i32> zeroinitializer, align 64

; Function Attrs: nounwind
define i32 @f0(i32 %a0) #0 {
b0:
  %v0 = alloca i32, align 4
  store i32 %a0, i32* %v0, align 4
  %v1 = call <16 x i32> @llvm.hexagon.V6.vd0()
  store <16 x i32> %v1, <16 x i32>* @g0, align 64
  ret i32 ptrtoint (<16 x i32>* @g0 to i32)
}

; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vd0() #1

attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone }