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<div class="section" id="hwreg">
<span id="amdgpu-synid-gfx7-hwreg"></span><h1>hwreg<a class="headerlink" href="#hwreg" title="Permalink to this headline">ΒΆ</a></h1>
<p>Bits of a hardware register being accessed.</p>
<p>The bits of this operand have the following meaning:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 18%" />
<col style="width: 53%" />
<col style="width: 30%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Bits</p></th>
<th class="head"><p>Description</p></th>
<th class="head"><p>Value Range</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>5:0</p></td>
<td><p>Register <em>id</em>.</p></td>
<td><p>0..63</p></td>
</tr>
<tr class="row-odd"><td><p>10:6</p></td>
<td><p>First bit <em>offset</em>.</p></td>
<td><p>0..31</p></td>
</tr>
<tr class="row-even"><td><p>15:11</p></td>
<td><p><em>Size</em> in bits.</p></td>
<td><p>1..32</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>This operand may be specified as one of the following:</p>
<ul>
<li><p>An <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a> or an <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute_expression</span></a>. The value must be in the range 0..0xFFFF.</p></li>
<li><p>An <em>hwreg</em> value described below.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 32%" />
<col style="width: 68%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Hwreg Value Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>hwreg({0..63})</p></td>
<td><p>All bits of a register indicated by its <em>id</em>.</p></td>
</tr>
<tr class="row-odd"><td><p>hwreg(<<em>name</em>>)</p></td>
<td><p>All bits of a register indicated by its <em>name</em>.</p></td>
</tr>
<tr class="row-even"><td><p>hwreg({0..63}, {0..31}, {1..32})</p></td>
<td><p>Register bits indicated by register <em>id</em>, first bit <em>offset</em> and <em>size</em>.</p></td>
</tr>
<tr class="row-odd"><td><p>hwreg(<<em>name</em>>, {0..31}, {1..32})</p></td>
<td><p>Register bits indicated by register <em>name</em>, first bit <em>offset</em> and <em>size</em>.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
</li>
</ul>
<p>Numeric values may be specified as positive <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>
or <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
<p>Defined register <em>names</em> include:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 31%" />
<col style="width: 69%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Name</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>HW_REG_MODE</p></td>
<td><p>Shader writeable mode bits.</p></td>
</tr>
<tr class="row-odd"><td><p>HW_REG_STATUS</p></td>
<td><p>Shader read-only status.</p></td>
</tr>
<tr class="row-even"><td><p>HW_REG_TRAPSTS</p></td>
<td><p>Trap status.</p></td>
</tr>
<tr class="row-odd"><td><p>HW_REG_HW_ID</p></td>
<td><p>Id of wave, simd, compute unit, etc.</p></td>
</tr>
<tr class="row-even"><td><p>HW_REG_GPR_ALLOC</p></td>
<td><p>Per-wave SGPR and VGPR allocation.</p></td>
</tr>
<tr class="row-odd"><td><p>HW_REG_LDS_ALLOC</p></td>
<td><p>Per-wave LDS allocation.</p></td>
</tr>
<tr class="row-even"><td><p>HW_REG_IB_STS</p></td>
<td><p>Counters of outstanding instructions.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Examples:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">reg</span> <span class="o">=</span> <span class="mi">1</span>
<span class="n">offset</span> <span class="o">=</span> <span class="mi">2</span>
<span class="n">size</span> <span class="o">=</span> <span class="mi">4</span>
<span class="n">hwreg_enc</span> <span class="o">=</span> <span class="n">reg</span> <span class="o">|</span> <span class="p">(</span><span class="n">offset</span> <span class="o"><<</span> <span class="mi">6</span><span class="p">)</span> <span class="o">|</span> <span class="p">((</span><span class="n">size</span> <span class="o">-</span> <span class="mi">1</span><span class="p">)</span> <span class="o"><<</span> <span class="mi">11</span><span class="p">)</span>
<span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="mh">0x1881</span>
<span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="n">hwreg_enc</span> <span class="o">//</span> <span class="n">the</span> <span class="n">same</span> <span class="k">as</span> <span class="n">above</span>
<span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="n">hwreg</span><span class="p">(</span><span class="mi">1</span><span class="p">,</span> <span class="mi">2</span><span class="p">,</span> <span class="mi">4</span><span class="p">)</span> <span class="o">//</span> <span class="n">the</span> <span class="n">same</span> <span class="k">as</span> <span class="n">above</span>
<span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="n">hwreg</span><span class="p">(</span><span class="n">reg</span><span class="p">,</span> <span class="n">offset</span><span class="p">,</span> <span class="n">size</span><span class="p">)</span> <span class="o">//</span> <span class="n">the</span> <span class="n">same</span> <span class="k">as</span> <span class="n">above</span>
<span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="n">hwreg</span><span class="p">(</span><span class="mi">15</span><span class="p">)</span>
<span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="n">hwreg</span><span class="p">(</span><span class="mi">51</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">31</span><span class="p">)</span>
<span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="n">hwreg</span><span class="p">(</span><span class="n">HW_REG_LDS_ALLOC</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
</pre></div>
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