1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
|
<!DOCTYPE html>
<html>
<head>
<meta charset="utf-8" />
<meta name="viewport" content="width=device-width, initial-scale=1.0" />
<title>Syntax of AMDGPU Instruction Operands — LLVM 13 documentation</title>
<link rel="stylesheet" href="_static/pygments.css" type="text/css" />
<link rel="stylesheet" href="_static/llvm-theme.css" type="text/css" />
<script id="documentation_options" data-url_root="./" src="_static/documentation_options.js"></script>
<script src="_static/jquery.js"></script>
<script src="_static/underscore.js"></script>
<script src="_static/doctools.js"></script>
<link rel="index" title="Index" href="genindex.html" />
<link rel="search" title="Search" href="search.html" />
<link rel="next" title="AMDGPU Instruction Syntax" href="AMDGPUInstructionSyntax.html" />
<link rel="prev" title="Syntax of AMDGPU Instruction Modifiers" href="AMDGPUModifierSyntax.html" />
<style type="text/css">
table.right { float: right; margin-left: 20px; }
table.right td { border: 1px solid #ccc; }
</style>
</head><body>
<div class="logo">
<a href="index.html">
<img src="_static/logo.png"
alt="LLVM Logo" width="250" height="88"/></a>
</div>
<div class="related" role="navigation" aria-label="related navigation">
<h3>Navigation</h3>
<ul>
<li class="right" style="margin-right: 10px">
<a href="genindex.html" title="General Index"
accesskey="I">index</a></li>
<li class="right" >
<a href="AMDGPUInstructionSyntax.html" title="AMDGPU Instruction Syntax"
accesskey="N">next</a> |</li>
<li class="right" >
<a href="AMDGPUModifierSyntax.html" title="Syntax of AMDGPU Instruction Modifiers"
accesskey="P">previous</a> |</li>
<li><a href="https://llvm.org/">LLVM Home</a> | </li>
<li><a href="index.html">Documentation</a>»</li>
<li class="nav-item nav-item-1"><a href="UserGuides.html" >User Guides</a> »</li>
<li class="nav-item nav-item-2"><a href="AMDGPUUsage.html" accesskey="U">User Guide for AMDGPU Backend</a> »</li>
<li class="nav-item nav-item-this"><a href="">Syntax of AMDGPU Instruction Operands</a></li>
</ul>
</div>
<div class="sphinxsidebar" role="navigation" aria-label="main navigation">
<div class="sphinxsidebarwrapper">
<h3>Documentation</h3>
<ul class="want-points">
<li><a href="https://llvm.org/docs/GettingStartedTutorials.html">Getting Started/Tutorials</a></li>
<li><a href="https://llvm.org/docs/UserGuides.html">User Guides</a></li>
<li><a href="https://llvm.org/docs/Reference.html">Reference</a></li>
</ul>
<h3>Getting Involved</h3>
<ul class="want-points">
<li><a href="https://llvm.org/docs/Contributing.html">Contributing to LLVM</a></li>
<li><a href="https://llvm.org/docs/HowToSubmitABug.html">Submitting Bug Reports</a></li>
<li><a href="https://llvm.org/docs/GettingInvolved.html#mailing-lists">Mailing Lists</a></li>
<li><a href="https://llvm.org/docs/GettingInvolved.html#irc">IRC</a></li>
<li><a href="https://llvm.org/docs/GettingInvolved.html#meetups-and-social-events">Meetups and Social Events</a></li>
</ul>
<h3>Additional Links</h3>
<ul class="want-points">
<li><a href="https://llvm.org/docs/FAQ.html">FAQ</a></li>
<li><a href="https://llvm.org/docs/Lexicon.html">Glossary</a></li>
<li><a href="https://llvm.org/pubs">Publications</a></li>
<li><a href="https://github.com/llvm/llvm-project//">Github Repository</a></li>
</ul>
<div role="note" aria-label="source link">
<h3>This Page</h3>
<ul class="this-page-menu">
<li><a href="_sources/AMDGPUOperandSyntax.rst.txt"
rel="nofollow">Show Source</a></li>
</ul>
</div>
<div id="searchbox" style="display: none" role="search">
<h3 id="searchlabel">Quick search</h3>
<div class="searchformwrapper">
<form class="search" action="search.html" method="get">
<input type="text" name="q" aria-labelledby="searchlabel" />
<input type="submit" value="Go" />
</form>
</div>
</div>
<script>$('#searchbox').show(0);</script>
</div>
</div>
<div class="document">
<div class="documentwrapper">
<div class="bodywrapper">
<div class="body" role="main">
<div class="section" id="syntax-of-amdgpu-instruction-operands">
<h1>Syntax of AMDGPU Instruction Operands<a class="headerlink" href="#syntax-of-amdgpu-instruction-operands" title="Permalink to this headline">¶</a></h1>
<div class="contents local topic" id="contents">
<ul class="simple">
<li><p><a class="reference internal" href="#conventions" id="id1">Conventions</a></p></li>
<li><p><a class="reference internal" href="#operands" id="id2">Operands</a></p>
<ul>
<li><p><a class="reference internal" href="#v" id="id3">v</a></p></li>
<li><p><a class="reference internal" href="#a" id="id4">a</a></p></li>
<li><p><a class="reference internal" href="#s" id="id5">s</a></p></li>
<li><p><a class="reference internal" href="#trap" id="id6">trap</a></p></li>
<li><p><a class="reference internal" href="#ttmp" id="id7">ttmp</a></p></li>
<li><p><a class="reference internal" href="#tba" id="id8">tba</a></p></li>
<li><p><a class="reference internal" href="#tma" id="id9">tma</a></p></li>
<li><p><a class="reference internal" href="#flat-scratch" id="id10">flat_scratch</a></p></li>
<li><p><a class="reference internal" href="#xnack-mask" id="id11">xnack_mask</a></p></li>
<li><p><a class="reference internal" href="#vcc" id="id12">vcc</a></p></li>
<li><p><a class="reference internal" href="#m0" id="id13">m0</a></p></li>
<li><p><a class="reference internal" href="#exec" id="id14">exec</a></p></li>
<li><p><a class="reference internal" href="#vccz" id="id15">vccz</a></p></li>
<li><p><a class="reference internal" href="#execz" id="id16">execz</a></p></li>
<li><p><a class="reference internal" href="#scc" id="id17">scc</a></p></li>
<li><p><a class="reference internal" href="#lds-direct" id="id18">lds_direct</a></p></li>
<li><p><a class="reference internal" href="#null" id="id19">null</a></p></li>
<li><p><a class="reference internal" href="#inline-constant" id="id20">inline constant</a></p>
<ul>
<li><p><a class="reference internal" href="#iconst" id="id21">iconst</a></p></li>
<li><p><a class="reference internal" href="#fconst" id="id22">fconst</a></p></li>
<li><p><a class="reference internal" href="#ival" id="id23">ival</a></p></li>
</ul>
</li>
<li><p><a class="reference internal" href="#literal" id="id24">literal</a></p></li>
<li><p><a class="reference internal" href="#uimm8" id="id25">uimm8</a></p></li>
<li><p><a class="reference internal" href="#uimm32" id="id26">uimm32</a></p></li>
<li><p><a class="reference internal" href="#uimm20" id="id27">uimm20</a></p></li>
<li><p><a class="reference internal" href="#simm21" id="id28">simm21</a></p></li>
<li><p><a class="reference internal" href="#off" id="id29">off</a></p></li>
</ul>
</li>
<li><p><a class="reference internal" href="#numbers" id="id30">Numbers</a></p>
<ul>
<li><p><a class="reference internal" href="#integer-numbers" id="id31">Integer Numbers</a></p></li>
<li><p><a class="reference internal" href="#floating-point-numbers" id="id32">Floating-Point Numbers</a></p></li>
</ul>
</li>
<li><p><a class="reference internal" href="#expressions" id="id33">Expressions</a></p>
<ul>
<li><p><a class="reference internal" href="#absolute-expressions" id="id34">Absolute Expressions</a></p></li>
<li><p><a class="reference internal" href="#relocatable-expressions" id="id35">Relocatable Expressions</a></p></li>
<li><p><a class="reference internal" href="#operands-and-operations" id="id36">Operands and Operations</a></p></li>
<li><p><a class="reference internal" href="#syntax-of-expressions" id="id37">Syntax of Expressions</a></p></li>
<li><p><a class="reference internal" href="#binary-operators" id="id38">Binary Operators</a></p></li>
<li><p><a class="reference internal" href="#unary-operators" id="id39">Unary Operators</a></p></li>
<li><p><a class="reference internal" href="#symbols" id="id40">Symbols</a></p></li>
</ul>
</li>
<li><p><a class="reference internal" href="#type-and-size-conversion" id="id41">Type and Size Conversion</a></p>
<ul>
<li><p><a class="reference internal" href="#conversion-of-integer-values" id="id42">Conversion of Integer Values</a></p></li>
<li><p><a class="reference internal" href="#conversion-of-floating-point-values" id="id43">Conversion of Floating-Point Values</a></p></li>
<li><p><a class="reference internal" href="#conversion-of-relocatable-values" id="id44">Conversion of Relocatable Values</a></p></li>
</ul>
</li>
</ul>
</div>
<div class="section" id="conventions">
<h2><a class="toc-backref" href="#id1">Conventions</a><a class="headerlink" href="#conventions" title="Permalink to this headline">¶</a></h2>
<p>The following notation is used throughout this document:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 20%" />
<col style="width: 80%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Notation</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>{0..N}</p></td>
<td><p>Any integer value in the range from 0 to N (inclusive).</p></td>
</tr>
<tr class="row-odd"><td><p><x></p></td>
<td><p>Syntax and meaning of <em>x</em> is explained elsewhere.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="operands">
<span id="amdgpu-syn-operands"></span><h2><a class="toc-backref" href="#id2">Operands</a><a class="headerlink" href="#operands" title="Permalink to this headline">¶</a></h2>
<div class="section" id="v">
<span id="amdgpu-synid-v"></span><h3><a class="toc-backref" href="#id3">v</a><a class="headerlink" href="#v" title="Permalink to this headline">¶</a></h3>
<p>Vector registers. There are 256 32-bit vector registers.</p>
<p>A sequence of <em>vector</em> registers may be used to operate with more than 32 bits of data.</p>
<p>Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 7, 8, 16 and 32 <em>vector</em> registers.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 43%" />
<col style="width: 57%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p><strong>v</strong><N></p></td>
<td><p>A single 32-bit <em>vector</em> register.</p>
<p><em>N</em> must be a decimal
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
</td>
</tr>
<tr class="row-odd"><td><p><strong>v[</strong><N><strong>]</strong></p></td>
<td><p>A single 32-bit <em>vector</em> register.</p>
<p><em>N</em> may be specified as an
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
</td>
</tr>
<tr class="row-even"><td><p><strong>v[</strong><N>:<K><strong>]</strong></p></td>
<td><p>A sequence of (<em>K-N+1</em>) <em>vector</em> registers.</p>
<p><em>N</em> and <em>K</em> may be specified as
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>
or <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
</td>
</tr>
<tr class="row-odd"><td><p><strong>[v</strong><N>, <strong>v</strong><N+1>, … <strong>v</strong><K><strong>]</strong></p></td>
<td><p>A sequence of (<em>K-N+1</em>) <em>vector</em> registers.</p>
<p>Register indices must be specified as decimal
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>.</p>
</td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Note: <em>N</em> and <em>K</em> must satisfy the following conditions:</p>
<ul class="simple">
<li><p><em>N</em> <= <em>K</em>.</p></li>
<li><p>0 <= <em>N</em> <= 255.</p></li>
<li><p>0 <= <em>K</em> <= 255.</p></li>
<li><p><em>K-N+1</em> must be equal to 1, 2, 3, 4, 5, 6, 7, 8, 16 or 32.</p></li>
</ul>
<p>GFX90A has an additional alignment requirement: pairs of <em>vector</em> registers must be even-aligned
(first register must be even).</p>
<p>Examples:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">v255</span>
<span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span>
<span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
<span class="n">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
<span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
<span class="n">v</span><span class="p">[</span><span class="mi">2</span><span class="o">*</span><span class="mi">2</span><span class="p">]</span>
<span class="n">v</span><span class="p">[</span><span class="mi">1</span><span class="o">-</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="o">-</span><span class="mi">1</span><span class="p">]</span>
<span class="p">[</span><span class="n">v252</span><span class="p">]</span>
<span class="p">[</span><span class="n">v252</span><span class="p">,</span><span class="n">v253</span><span class="p">,</span><span class="n">v254</span><span class="p">,</span><span class="n">v255</span><span class="p">]</span>
</pre></div>
</div>
<p id="amdgpu-synid-nsa">GFX10 <em>Image</em> instructions may use special <em>NSA</em> (Non-Sequential Address) syntax for <em>image addresses</em>:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 43%" />
<col style="width: 57%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p><strong>[Vm</strong>, <strong>Vn</strong>, … <strong>Vk</strong><strong>]</strong></p></td>
<td><p>A sequence of 32-bit <em>vector</em> registers.
Each register may be specified using syntax
defined <a class="reference internal" href="#amdgpu-synid-v"><span class="std std-ref">above</span></a>.</p>
<p>In contrast with standard syntax, registers
in <em>NSA</em> sequence are not required to have
consecutive indices. Moreover, the same register
may appear in the list more than once.</p>
</td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Examples:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="p">[</span><span class="n">v32</span><span class="p">,</span><span class="n">v1</span><span class="p">,</span><span class="n">v</span><span class="p">[</span><span class="mi">2</span><span class="p">]]</span>
<span class="p">[</span><span class="n">v</span><span class="p">[</span><span class="mi">32</span><span class="p">],</span><span class="n">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">1</span><span class="p">],[</span><span class="n">v2</span><span class="p">]]</span>
<span class="p">[</span><span class="n">v4</span><span class="p">,</span><span class="n">v4</span><span class="p">,</span><span class="n">v4</span><span class="p">,</span><span class="n">v4</span><span class="p">]</span>
</pre></div>
</div>
</div>
<div class="section" id="a">
<span id="amdgpu-synid-a"></span><h3><a class="toc-backref" href="#id4">a</a><a class="headerlink" href="#a" title="Permalink to this headline">¶</a></h3>
<p>Accumulator registers. There are 256 32-bit accumulator registers.</p>
<p>A sequence of <em>accumulator</em> registers may be used to operate with more than 32 bits of data.</p>
<p>Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 7, 8, 16 and 32 <em>accumulator</em> registers.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 29%" />
<col style="width: 32%" />
<col style="width: 39%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>An Alternative Syntax (SP3)</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p><strong>a</strong><N></p></td>
<td><p><strong>acc</strong><N></p></td>
<td><p>A single 32-bit <em>accumulator</em> register.</p>
<p><em>N</em> must be a decimal
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
</td>
</tr>
<tr class="row-odd"><td><p><strong>a[</strong><N><strong>]</strong></p></td>
<td><p><strong>acc[</strong><N><strong>]</strong></p></td>
<td><p>A single 32-bit <em>accumulator</em> register.</p>
<p><em>N</em> may be specified as an
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
</td>
</tr>
<tr class="row-even"><td><p><strong>a[</strong><N>:<K><strong>]</strong></p></td>
<td><p><strong>acc[</strong><N>:<K><strong>]</strong></p></td>
<td><p>A sequence of (<em>K-N+1</em>) <em>accumulator</em> registers.</p>
<p><em>N</em> and <em>K</em> may be specified as
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>
or <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
</td>
</tr>
<tr class="row-odd"><td><p><strong>[a</strong><N>, <strong>a</strong><N+1>, … <strong>a</strong><K><strong>]</strong></p></td>
<td><p><strong>[acc</strong><N>, <strong>acc</strong><N+1>, … <strong>acc</strong><K><strong>]</strong></p></td>
<td><p>A sequence of (<em>K-N+1</em>) <em>accumulator</em> registers.</p>
<p>Register indices must be specified as decimal
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>.</p>
</td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Note: <em>N</em> and <em>K</em> must satisfy the following conditions:</p>
<ul class="simple">
<li><p><em>N</em> <= <em>K</em>.</p></li>
<li><p>0 <= <em>N</em> <= 255.</p></li>
<li><p>0 <= <em>K</em> <= 255.</p></li>
<li><p><em>K-N+1</em> must be equal to 1, 2, 3, 4, 5, 6, 7, 8, 16 or 32.</p></li>
</ul>
<p>GFX90A has an additional alignment requirement: pairs of <em>accumulator</em> registers must be even-aligned
(first register must be even).</p>
<p>Examples:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">a255</span>
<span class="n">a</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span>
<span class="n">a</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
<span class="n">a</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
<span class="n">a</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
<span class="n">a</span><span class="p">[</span><span class="mi">2</span><span class="o">*</span><span class="mi">2</span><span class="p">]</span>
<span class="n">a</span><span class="p">[</span><span class="mi">1</span><span class="o">-</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="o">-</span><span class="mi">1</span><span class="p">]</span>
<span class="p">[</span><span class="n">a252</span><span class="p">]</span>
<span class="p">[</span><span class="n">a252</span><span class="p">,</span><span class="n">a253</span><span class="p">,</span><span class="n">a254</span><span class="p">,</span><span class="n">a255</span><span class="p">]</span>
<span class="n">acc0</span>
<span class="n">acc</span><span class="p">[</span><span class="mi">1</span><span class="p">]</span>
<span class="p">[</span><span class="n">acc250</span><span class="p">]</span>
<span class="p">[</span><span class="n">acc2</span><span class="p">,</span><span class="n">acc3</span><span class="p">]</span>
</pre></div>
</div>
</div>
<div class="section" id="s">
<span id="amdgpu-synid-s"></span><h3><a class="toc-backref" href="#id5">s</a><a class="headerlink" href="#s" title="Permalink to this headline">¶</a></h3>
<p>Scalar 32-bit registers. The number of available <em>scalar</em> registers depends on GPU:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 20%" />
<col style="width: 80%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>GPU</p></th>
<th class="head"><p>Number of <em>scalar</em> registers</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>GFX7</p></td>
<td><p>104</p></td>
</tr>
<tr class="row-odd"><td><p>GFX8</p></td>
<td><p>102</p></td>
</tr>
<tr class="row-even"><td><p>GFX9</p></td>
<td><p>102</p></td>
</tr>
<tr class="row-odd"><td><p>GFX10</p></td>
<td><p>106</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>A sequence of <em>scalar</em> registers may be used to operate with more than 32 bits of data.
Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 7, 8, 16 and 32 <em>scalar</em> registers.</p>
<p>Pairs of <em>scalar</em> registers must be even-aligned (first register must be even).
Sequences of 4 and more <em>scalar</em> registers must be quad-aligned.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 45%" />
<col style="width: 55%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p><strong>s</strong><N></p></td>
<td><p>A single 32-bit <em>scalar</em> register.</p>
<p><em>N</em> must be a decimal
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
</td>
</tr>
<tr class="row-odd"><td><p><strong>s[</strong><N><strong>]</strong></p></td>
<td><p>A single 32-bit <em>scalar</em> register.</p>
<p><em>N</em> may be specified as an
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
</td>
</tr>
<tr class="row-even"><td><p><strong>s[</strong><N>:<K><strong>]</strong></p></td>
<td><p>A sequence of (<em>K-N+1</em>) <em>scalar</em> registers.</p>
<p><em>N</em> and <em>K</em> may be specified as
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>
or <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
</td>
</tr>
<tr class="row-odd"><td><p><strong>[s</strong><N>, <strong>s</strong><N+1>, … <strong>s</strong><K><strong>]</strong></p></td>
<td><p>A sequence of (<em>K-N+1</em>) <em>scalar</em> registers.</p>
<p>Register indices must be specified as decimal
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>.</p>
</td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Note: <em>N</em> and <em>K</em> must satisfy the following conditions:</p>
<ul class="simple">
<li><p><em>N</em> must be properly aligned based on sequence size.</p></li>
<li><p><em>N</em> <= <em>K</em>.</p></li>
<li><p>0 <= <em>N</em> < <em>SMAX</em>, where <em>SMAX</em> is the number of available <em>scalar</em> registers.</p></li>
<li><p>0 <= <em>K</em> < <em>SMAX</em>, where <em>SMAX</em> is the number of available <em>scalar</em> registers.</p></li>
<li><p><em>K-N+1</em> must be equal to 1, 2, 3, 4, 5, 6, 7, 8, 16 or 32.</p></li>
</ul>
<p>Examples:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">s0</span>
<span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span>
<span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
<span class="n">s</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
<span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
<span class="n">s</span><span class="p">[</span><span class="mi">2</span><span class="o">*</span><span class="mi">2</span><span class="p">]</span>
<span class="n">s</span><span class="p">[</span><span class="mi">1</span><span class="o">-</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="o">-</span><span class="mi">1</span><span class="p">]</span>
<span class="p">[</span><span class="n">s4</span><span class="p">]</span>
<span class="p">[</span><span class="n">s4</span><span class="p">,</span><span class="n">s5</span><span class="p">,</span><span class="n">s6</span><span class="p">,</span><span class="n">s7</span><span class="p">]</span>
</pre></div>
</div>
<p>Examples of <em>scalar</em> registers with an invalid alignment:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">s</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">]</span>
<span class="n">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
</pre></div>
</div>
</div>
<div class="section" id="trap">
<span id="amdgpu-synid-trap"></span><h3><a class="toc-backref" href="#id6">trap</a><a class="headerlink" href="#trap" title="Permalink to this headline">¶</a></h3>
<p>A set of trap handler registers:</p>
<ul class="simple">
<li><p><a class="reference internal" href="#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></p></li>
<li><p><a class="reference internal" href="#amdgpu-synid-tba"><span class="std std-ref">tba</span></a></p></li>
<li><p><a class="reference internal" href="#amdgpu-synid-tma"><span class="std std-ref">tma</span></a></p></li>
</ul>
</div>
<div class="section" id="ttmp">
<span id="amdgpu-synid-ttmp"></span><h3><a class="toc-backref" href="#id7">ttmp</a><a class="headerlink" href="#ttmp" title="Permalink to this headline">¶</a></h3>
<p>Trap handler temporary scalar registers, 32-bits wide.
The number of available <em>ttmp</em> registers depends on GPU:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 21%" />
<col style="width: 79%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>GPU</p></th>
<th class="head"><p>Number of <em>ttmp</em> registers</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>GFX7</p></td>
<td><p>12</p></td>
</tr>
<tr class="row-odd"><td><p>GFX8</p></td>
<td><p>12</p></td>
</tr>
<tr class="row-even"><td><p>GFX9</p></td>
<td><p>16</p></td>
</tr>
<tr class="row-odd"><td><p>GFX10</p></td>
<td><p>16</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>A sequence of <em>ttmp</em> registers may be used to operate with more than 32 bits of data.
Assembler currently supports sequences of 1, 2, 3, 4, 5, 6, 7, 8 and 16 <em>ttmp</em> registers.</p>
<p>Pairs of <em>ttmp</em> registers must be even-aligned (first register must be even).
Sequences of 4 and more <em>ttmp</em> registers must be quad-aligned.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 47%" />
<col style="width: 53%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p><strong>ttmp</strong><N></p></td>
<td><p>A single 32-bit <em>ttmp</em> register.</p>
<p><em>N</em> must be a decimal
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
</td>
</tr>
<tr class="row-odd"><td><p><strong>ttmp[</strong><N><strong>]</strong></p></td>
<td><p>A single 32-bit <em>ttmp</em> register.</p>
<p><em>N</em> may be specified as an
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
</td>
</tr>
<tr class="row-even"><td><p><strong>ttmp[</strong><N>:<K><strong>]</strong></p></td>
<td><p>A sequence of (<em>K-N+1</em>) <em>ttmp</em> registers.</p>
<p><em>N</em> and <em>K</em> may be specified as
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>
or <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
</td>
</tr>
<tr class="row-odd"><td><p><strong>[ttmp</strong><N>, <strong>ttmp</strong><N+1>, … <strong>ttmp</strong><K><strong>]</strong></p></td>
<td><p>A sequence of (<em>K-N+1</em>) <em>ttmp</em> registers.</p>
<p>Register indices must be specified as decimal
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>.</p>
</td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Note: <em>N</em> and <em>K</em> must satisfy the following conditions:</p>
<ul class="simple">
<li><p><em>N</em> must be properly aligned based on sequence size.</p></li>
<li><p><em>N</em> <= <em>K</em>.</p></li>
<li><p>0 <= <em>N</em> < <em>TMAX</em>, where <em>TMAX</em> is the number of available <em>ttmp</em> registers.</p></li>
<li><p>0 <= <em>K</em> < <em>TMAX</em>, where <em>TMAX</em> is the number of available <em>ttmp</em> registers.</p></li>
<li><p><em>K-N+1</em> must be equal to 1, 2, 3, 4, 5, 6, 7, 8 or 16.</p></li>
</ul>
<p>Examples:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">ttmp0</span>
<span class="n">ttmp</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span>
<span class="n">ttmp</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
<span class="n">ttmp</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
<span class="n">ttmp</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
<span class="n">ttmp</span><span class="p">[</span><span class="mi">2</span><span class="o">*</span><span class="mi">2</span><span class="p">]</span>
<span class="n">ttmp</span><span class="p">[</span><span class="mi">1</span><span class="o">-</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="o">-</span><span class="mi">1</span><span class="p">]</span>
<span class="p">[</span><span class="n">ttmp4</span><span class="p">]</span>
<span class="p">[</span><span class="n">ttmp4</span><span class="p">,</span><span class="n">ttmp5</span><span class="p">,</span><span class="n">ttmp6</span><span class="p">,</span><span class="n">ttmp7</span><span class="p">]</span>
</pre></div>
</div>
<p>Examples of <em>ttmp</em> registers with an invalid alignment:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">ttmp</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">]</span>
<span class="n">ttmp</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
</pre></div>
</div>
</div>
<div class="section" id="tba">
<span id="amdgpu-synid-tba"></span><h3><a class="toc-backref" href="#id8">tba</a><a class="headerlink" href="#tba" title="Permalink to this headline">¶</a></h3>
<p>Trap base address, 64-bits wide. Holds the pointer to the current trap handler program.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 18%" />
<col style="width: 70%" />
<col style="width: 13%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
<th class="head"><p>Availability</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>tba</p></td>
<td><p>64-bit <em>trap base address</em> register.</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
<tr class="row-odd"><td><p>[tba]</p></td>
<td><p>64-bit <em>trap base address</em> register (an SP3 syntax).</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
<tr class="row-even"><td><p>[tba_lo,tba_hi]</p></td>
<td><p>64-bit <em>trap base address</em> register (an SP3 syntax).</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>High and low 32 bits of <em>trap base address</em> may be accessed as separate registers:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 18%" />
<col style="width: 70%" />
<col style="width: 13%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
<th class="head"><p>Availability</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>tba_lo</p></td>
<td><p>Low 32 bits of <em>trap base address</em> register.</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
<tr class="row-odd"><td><p>tba_hi</p></td>
<td><p>High 32 bits of <em>trap base address</em> register.</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
<tr class="row-even"><td><p>[tba_lo]</p></td>
<td><p>Low 32 bits of <em>trap base address</em> register (an SP3 syntax).</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
<tr class="row-odd"><td><p>[tba_hi]</p></td>
<td><p>High 32 bits of <em>trap base address</em> register (an SP3 syntax).</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Note that <em>tba</em>, <em>tba_lo</em> and <em>tba_hi</em> are not accessible as assembler registers in GFX9 and GFX10,
but <em>tba</em> is readable/writable with the help of <em>s_get_reg</em> and <em>s_set_reg</em> instructions.</p>
</div>
<div class="section" id="tma">
<span id="amdgpu-synid-tma"></span><h3><a class="toc-backref" href="#id9">tma</a><a class="headerlink" href="#tma" title="Permalink to this headline">¶</a></h3>
<p>Trap memory address, 64-bits wide.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 16%" />
<col style="width: 67%" />
<col style="width: 17%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
<th class="head"><p>Availability</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>tma</p></td>
<td><p>64-bit <em>trap memory address</em> register.</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
<tr class="row-odd"><td><p>[tma]</p></td>
<td><p>64-bit <em>trap memory address</em> register (an SP3 syntax).</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
<tr class="row-even"><td><p>[tma_lo,tma_hi]</p></td>
<td><p>64-bit <em>trap memory address</em> register (an SP3 syntax).</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>High and low 32 bits of <em>trap memory address</em> may be accessed as separate registers:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 16%" />
<col style="width: 67%" />
<col style="width: 17%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
<th class="head"><p>Availability</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>tma_lo</p></td>
<td><p>Low 32 bits of <em>trap memory address</em> register.</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
<tr class="row-odd"><td><p>tma_hi</p></td>
<td><p>High 32 bits of <em>trap memory address</em> register.</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
<tr class="row-even"><td><p>[tma_lo]</p></td>
<td><p>Low 32 bits of <em>trap memory address</em> register (an SP3 syntax).</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
<tr class="row-odd"><td><p>[tma_hi]</p></td>
<td><p>High 32 bits of <em>trap memory address</em> register (an SP3 syntax).</p></td>
<td><p>GFX7, GFX8</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Note that <em>tma</em>, <em>tma_lo</em> and <em>tma_hi</em> are not accessible as assembler registers in GFX9 and GFX10,
but <em>tma</em> is readable/writable with the help of <em>s_get_reg</em> and <em>s_set_reg</em> instructions.</p>
</div>
<div class="section" id="flat-scratch">
<span id="amdgpu-synid-flat-scratch"></span><h3><a class="toc-backref" href="#id10">flat_scratch</a><a class="headerlink" href="#flat-scratch" title="Permalink to this headline">¶</a></h3>
<p>Flat scratch address, 64-bits wide. Holds the base address of scratch memory.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 35%" />
<col style="width: 65%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>flat_scratch</p></td>
<td><p>64-bit <em>flat scratch</em> address register.</p></td>
</tr>
<tr class="row-odd"><td><p>[flat_scratch]</p></td>
<td><p>64-bit <em>flat scratch</em> address register (an SP3 syntax).</p></td>
</tr>
<tr class="row-even"><td><p>[flat_scratch_lo,flat_scratch_hi]</p></td>
<td><p>64-bit <em>flat scratch</em> address register (an SP3 syntax).</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>High and low 32 bits of <em>flat scratch</em> address may be accessed as separate registers:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 26%" />
<col style="width: 74%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>flat_scratch_lo</p></td>
<td><p>Low 32 bits of <em>flat scratch</em> address register.</p></td>
</tr>
<tr class="row-odd"><td><p>flat_scratch_hi</p></td>
<td><p>High 32 bits of <em>flat scratch</em> address register.</p></td>
</tr>
<tr class="row-even"><td><p>[flat_scratch_lo]</p></td>
<td><p>Low 32 bits of <em>flat scratch</em> address register (an SP3 syntax).</p></td>
</tr>
<tr class="row-odd"><td><p>[flat_scratch_hi]</p></td>
<td><p>High 32 bits of <em>flat scratch</em> address register (an SP3 syntax).</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Note that <em>flat_scratch</em>, <em>flat_scratch_lo</em> and <em>flat_scratch_hi</em> are not accessible as assembler
registers in GFX10, but <em>flat_scratch</em> is readable/writable with the help of
<em>s_get_reg</em> and <em>s_set_reg</em> instructions.</p>
</div>
<div class="section" id="xnack-mask">
<span id="amdgpu-synid-xnack-mask"></span><span id="amdgpu-synid-xnack"></span><h3><a class="toc-backref" href="#id11">xnack_mask</a><a class="headerlink" href="#xnack-mask" title="Permalink to this headline">¶</a></h3>
<p>Xnack mask, 64-bits wide. Holds a 64-bit mask of which threads
received an <em>XNACK</em> due to a vector memory operation.</p>
<div class="admonition warning">
<p class="admonition-title">Warning</p>
<p>GFX7 does not support <em>xnack</em> feature. For availability of this feature in other GPUs, refer <a class="reference internal" href="AMDGPUUsage.html#amdgpu-processors"><span class="std std-ref">this table</span></a>.</p>
</div>
<p></p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 36%" />
<col style="width: 64%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>xnack_mask</p></td>
<td><p>64-bit <em>xnack mask</em> register.</p></td>
</tr>
<tr class="row-odd"><td><p>[xnack_mask]</p></td>
<td><p>64-bit <em>xnack mask</em> register (an SP3 syntax).</p></td>
</tr>
<tr class="row-even"><td><p>[xnack_mask_lo,xnack_mask_hi]</p></td>
<td><p>64-bit <em>xnack mask</em> register (an SP3 syntax).</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>High and low 32 bits of <em>xnack mask</em> may be accessed as separate registers:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 25%" />
<col style="width: 75%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>xnack_mask_lo</p></td>
<td><p>Low 32 bits of <em>xnack mask</em> register.</p></td>
</tr>
<tr class="row-odd"><td><p>xnack_mask_hi</p></td>
<td><p>High 32 bits of <em>xnack mask</em> register.</p></td>
</tr>
<tr class="row-even"><td><p>[xnack_mask_lo]</p></td>
<td><p>Low 32 bits of <em>xnack mask</em> register (an SP3 syntax).</p></td>
</tr>
<tr class="row-odd"><td><p>[xnack_mask_hi]</p></td>
<td><p>High 32 bits of <em>xnack mask</em> register (an SP3 syntax).</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Note that <em>xnack_mask</em>, <em>xnack_mask_lo</em> and <em>xnack_mask_hi</em> are not accessible as assembler
registers in GFX10, but <em>xnack_mask</em> is readable/writable with the help of
<em>s_get_reg</em> and <em>s_set_reg</em> instructions.</p>
</div>
<div class="section" id="vcc">
<span id="amdgpu-synid-vcc-lo"></span><span id="amdgpu-synid-vcc"></span><h3><a class="toc-backref" href="#id12">vcc</a><a class="headerlink" href="#vcc" title="Permalink to this headline">¶</a></h3>
<p>Vector condition code, 64-bits wide. A bit mask with one bit per thread;
it holds the result of a vector compare operation.</p>
<p>Note that GFX10 H/W does not use high 32 bits of <em>vcc</em> in <em>wave32</em> mode.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 18%" />
<col style="width: 82%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>vcc</p></td>
<td><p>64-bit <em>vector condition code</em> register.</p></td>
</tr>
<tr class="row-odd"><td><p>[vcc]</p></td>
<td><p>64-bit <em>vector condition code</em> register (an SP3 syntax).</p></td>
</tr>
<tr class="row-even"><td><p>[vcc_lo,vcc_hi]</p></td>
<td><p>64-bit <em>vector condition code</em> register (an SP3 syntax).</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>High and low 32 bits of <em>vector condition code</em> may be accessed as separate registers:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 18%" />
<col style="width: 82%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>vcc_lo</p></td>
<td><p>Low 32 bits of <em>vector condition code</em> register.</p></td>
</tr>
<tr class="row-odd"><td><p>vcc_hi</p></td>
<td><p>High 32 bits of <em>vector condition code</em> register.</p></td>
</tr>
<tr class="row-even"><td><p>[vcc_lo]</p></td>
<td><p>Low 32 bits of <em>vector condition code</em> register (an SP3 syntax).</p></td>
</tr>
<tr class="row-odd"><td><p>[vcc_hi]</p></td>
<td><p>High 32 bits of <em>vector condition code</em> register (an SP3 syntax).</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="m0">
<span id="amdgpu-synid-m0"></span><h3><a class="toc-backref" href="#id13">m0</a><a class="headerlink" href="#m0" title="Permalink to this headline">¶</a></h3>
<p>A 32-bit memory register. It has various uses,
including register indexing and bounds checking.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 18%" />
<col style="width: 82%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>m0</p></td>
<td><p>A 32-bit <em>memory</em> register.</p></td>
</tr>
<tr class="row-odd"><td><p>[m0]</p></td>
<td><p>A 32-bit <em>memory</em> register (an SP3 syntax).</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="exec">
<span id="amdgpu-synid-exec"></span><h3><a class="toc-backref" href="#id14">exec</a><a class="headerlink" href="#exec" title="Permalink to this headline">¶</a></h3>
<p>Execute mask, 64-bits wide. A bit mask with one bit per thread,
which is applied to vector instructions and controls which threads execute
and which ignore the instruction.</p>
<p>Note that GFX10 H/W does not use high 32 bits of <em>exec</em> in <em>wave32</em> mode.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 24%" />
<col style="width: 76%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>exec</p></td>
<td><p>64-bit <em>execute mask</em> register.</p></td>
</tr>
<tr class="row-odd"><td><p>[exec]</p></td>
<td><p>64-bit <em>execute mask</em> register (an SP3 syntax).</p></td>
</tr>
<tr class="row-even"><td><p>[exec_lo,exec_hi]</p></td>
<td><p>64-bit <em>execute mask</em> register (an SP3 syntax).</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>High and low 32 bits of <em>execute mask</em> may be accessed as separate registers:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 24%" />
<col style="width: 76%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>exec_lo</p></td>
<td><p>Low 32 bits of <em>execute mask</em> register.</p></td>
</tr>
<tr class="row-odd"><td><p>exec_hi</p></td>
<td><p>High 32 bits of <em>execute mask</em> register.</p></td>
</tr>
<tr class="row-even"><td><p>[exec_lo]</p></td>
<td><p>Low 32 bits of <em>execute mask</em> register (an SP3 syntax).</p></td>
</tr>
<tr class="row-odd"><td><p>[exec_hi]</p></td>
<td><p>High 32 bits of <em>execute mask</em> register (an SP3 syntax).</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="vccz">
<span id="amdgpu-synid-vccz"></span><h3><a class="toc-backref" href="#id15">vccz</a><a class="headerlink" href="#vccz" title="Permalink to this headline">¶</a></h3>
<p>A single bit flag indicating that the <a class="reference internal" href="#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a> is all zeros.</p>
<p>Note: when GFX10 operates in <em>wave32</em> mode, this register reflects state of <a class="reference internal" href="#amdgpu-synid-vcc-lo"><span class="std std-ref">vcc_lo</span></a>.</p>
</div>
<div class="section" id="execz">
<span id="amdgpu-synid-execz"></span><h3><a class="toc-backref" href="#id16">execz</a><a class="headerlink" href="#execz" title="Permalink to this headline">¶</a></h3>
<p>A single bit flag indicating that the <a class="reference internal" href="#amdgpu-synid-exec"><span class="std std-ref">exec</span></a> is all zeros.</p>
<p>Note: when GFX10 operates in <em>wave32</em> mode, this register reflects state of <a class="reference internal" href="#amdgpu-synid-exec"><span class="std std-ref">exec_lo</span></a>.</p>
</div>
<div class="section" id="scc">
<span id="amdgpu-synid-scc"></span><h3><a class="toc-backref" href="#id17">scc</a><a class="headerlink" href="#scc" title="Permalink to this headline">¶</a></h3>
<p>A single bit flag indicating the result of a scalar compare operation.</p>
</div>
<div class="section" id="lds-direct">
<span id="amdgpu-synid-lds-direct"></span><h3><a class="toc-backref" href="#id18">lds_direct</a><a class="headerlink" href="#lds-direct" title="Permalink to this headline">¶</a></h3>
<p>A special operand which supplies a 32-bit value
fetched from <em>LDS</em> memory using <a class="reference internal" href="#amdgpu-synid-m0"><span class="std std-ref">m0</span></a> as an address.</p>
</div>
<div class="section" id="null">
<span id="amdgpu-synid-null"></span><h3><a class="toc-backref" href="#id19">null</a><a class="headerlink" href="#null" title="Permalink to this headline">¶</a></h3>
<p>This is a special operand which may be used as a source or a destination.</p>
<p>When used as a destination, the result of the operation is discarded.</p>
<p>When used as a source, it supplies zero value.</p>
<p>GFX10 only.</p>
<div class="admonition warning">
<p class="admonition-title">Warning</p>
<p>Due to a H/W bug, this operand cannot be used with VALU instructions in first generation of GFX10.</p>
</div>
</div>
<div class="section" id="inline-constant">
<span id="amdgpu-synid-constant"></span><h3><a class="toc-backref" href="#id20">inline constant</a><a class="headerlink" href="#inline-constant" title="Permalink to this headline">¶</a></h3>
<p>An <em>inline constant</em> is an integer or a floating-point value encoded as a part of an instruction.
Compare <em>inline constants</em> with <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a>.</p>
<p>Inline constants include:</p>
<ul class="simple">
<li><p><a class="reference internal" href="#amdgpu-synid-iconst"><span class="std std-ref">iconst</span></a></p></li>
<li><p><a class="reference internal" href="#amdgpu-synid-fconst"><span class="std std-ref">fconst</span></a></p></li>
<li><p><a class="reference internal" href="#amdgpu-synid-ival"><span class="std std-ref">ival</span></a></p></li>
</ul>
<p>If a number may be encoded as either
a <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literal</span></a> or
a <a class="reference internal" href="#amdgpu-synid-constant"><span class="std std-ref">constant</span></a>,
assembler selects the latter encoding as more efficient.</p>
<div class="section" id="iconst">
<span id="amdgpu-synid-iconst"></span><h4><a class="toc-backref" href="#id21">iconst</a><a class="headerlink" href="#iconst" title="Permalink to this headline">¶</a></h4>
<p>An <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a> or
an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>
encoded as an <em>inline constant</em>.</p>
<p>Only a small fraction of integer numbers may be encoded as <em>inline constants</em>.
They are enumerated in the table below.
Other integer numbers have to be encoded as <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a>.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 49%" />
<col style="width: 51%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Value</p></th>
<th class="head"><p>Note</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>{0..64}</p></td>
<td><p>Positive integer inline constants.</p></td>
</tr>
<tr class="row-odd"><td><p>{-16..-1}</p></td>
<td><p>Negative integer inline constants.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<div class="admonition warning">
<p class="admonition-title">Warning</p>
<p>GFX7 does not support inline constants for <em>f16</em> operands.</p>
</div>
</div>
<div class="section" id="fconst">
<span id="amdgpu-synid-fconst"></span><h4><a class="toc-backref" href="#id22">fconst</a><a class="headerlink" href="#fconst" title="Permalink to this headline">¶</a></h4>
<p>A <a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point number</span></a>
encoded as an <em>inline constant</em>.</p>
<p>Only a small fraction of floating-point numbers may be encoded as <em>inline constants</em>.
They are enumerated in the table below.
Other floating-point numbers have to be encoded as <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a>.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 23%" />
<col style="width: 58%" />
<col style="width: 20%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Value</p></th>
<th class="head"><p>Note</p></th>
<th class="head"><p>Availability</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>0.0</p></td>
<td><p>The same as integer constant 0.</p></td>
<td><p>All GPUs</p></td>
</tr>
<tr class="row-odd"><td><p>0.5</p></td>
<td><p>Floating-point constant 0.5</p></td>
<td><p>All GPUs</p></td>
</tr>
<tr class="row-even"><td><p>1.0</p></td>
<td><p>Floating-point constant 1.0</p></td>
<td><p>All GPUs</p></td>
</tr>
<tr class="row-odd"><td><p>2.0</p></td>
<td><p>Floating-point constant 2.0</p></td>
<td><p>All GPUs</p></td>
</tr>
<tr class="row-even"><td><p>4.0</p></td>
<td><p>Floating-point constant 4.0</p></td>
<td><p>All GPUs</p></td>
</tr>
<tr class="row-odd"><td><p>-0.5</p></td>
<td><p>Floating-point constant -0.5</p></td>
<td><p>All GPUs</p></td>
</tr>
<tr class="row-even"><td><p>-1.0</p></td>
<td><p>Floating-point constant -1.0</p></td>
<td><p>All GPUs</p></td>
</tr>
<tr class="row-odd"><td><p>-2.0</p></td>
<td><p>Floating-point constant -2.0</p></td>
<td><p>All GPUs</p></td>
</tr>
<tr class="row-even"><td><p>-4.0</p></td>
<td><p>Floating-point constant -4.0</p></td>
<td><p>All GPUs</p></td>
</tr>
<tr class="row-odd"><td><p>0.1592</p></td>
<td><p>1.0/(2.0*pi). Use only for 16-bit operands.</p></td>
<td><p>GFX8, GFX9, GFX10</p></td>
</tr>
<tr class="row-even"><td><p>0.15915494</p></td>
<td><p>1.0/(2.0*pi). Use only for 16- and 32-bit operands.</p></td>
<td><p>GFX8, GFX9, GFX10</p></td>
</tr>
<tr class="row-odd"><td><p>0.15915494309189532</p></td>
<td><p>1.0/(2.0*pi).</p></td>
<td><p>GFX8, GFX9, GFX10</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<div class="admonition warning">
<p class="admonition-title">Warning</p>
<p>Floating-point inline constants cannot be used with <em>16-bit integer</em> operands. Assembler will attempt to encode these values as literals.</p>
</div>
<div class="admonition warning">
<p class="admonition-title">Warning</p>
<p>GFX7 does not support inline constants for <em>f16</em> operands.</p>
</div>
</div>
<div class="section" id="ival">
<span id="amdgpu-synid-ival"></span><h4><a class="toc-backref" href="#id23">ival</a><a class="headerlink" href="#ival" title="Permalink to this headline">¶</a></h4>
<p>A symbolic operand encoded as an <em>inline constant</em>.
These operands provide read-only access to H/W registers.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 28%" />
<col style="width: 56%" />
<col style="width: 15%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Note</p></th>
<th class="head"><p>Availability</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>shared_base</p></td>
<td><p>Base address of shared memory region.</p></td>
<td><p>GFX9, GFX10</p></td>
</tr>
<tr class="row-odd"><td><p>shared_limit</p></td>
<td><p>Address of the end of shared memory region.</p></td>
<td><p>GFX9, GFX10</p></td>
</tr>
<tr class="row-even"><td><p>private_base</p></td>
<td><p>Base address of private memory region.</p></td>
<td><p>GFX9, GFX10</p></td>
</tr>
<tr class="row-odd"><td><p>private_limit</p></td>
<td><p>Address of the end of private memory region.</p></td>
<td><p>GFX9, GFX10</p></td>
</tr>
<tr class="row-even"><td><p>pops_exiting_wave_id</p></td>
<td><p>A dedicated counter for POPS.</p></td>
<td><p>GFX9, GFX10</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
</div>
<div class="section" id="literal">
<span id="amdgpu-synid-literal"></span><h3><a class="toc-backref" href="#id24">literal</a><a class="headerlink" href="#literal" title="Permalink to this headline">¶</a></h3>
<p>A <em>literal</em> is a 64-bit value encoded as a separate 32-bit dword in the instruction stream.
Compare <em>literals</em> with <a class="reference internal" href="#amdgpu-synid-constant"><span class="std std-ref">inline constants</span></a>.</p>
<p>If a number may be encoded as either
a <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literal</span></a> or
an <a class="reference internal" href="#amdgpu-synid-constant"><span class="std std-ref">inline constant</span></a>,
assembler selects the latter encoding as more efficient.</p>
<p>Literals may be specified as <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>,
<a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a>,
<a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a> or
<a class="reference internal" href="#amdgpu-synid-relocatable-expression"><span class="std std-ref">relocatable expressions</span></a>.</p>
<p>An instruction may use only one literal but several operands may refer the same literal.</p>
</div>
<div class="section" id="uimm8">
<span id="amdgpu-synid-uimm8"></span><h3><a class="toc-backref" href="#id25">uimm8</a><a class="headerlink" href="#uimm8" title="Permalink to this headline">¶</a></h3>
<p>A 8-bit <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.
The value must be in the range 0..0xFF.</p>
</div>
<div class="section" id="uimm32">
<span id="amdgpu-synid-uimm32"></span><h3><a class="toc-backref" href="#id26">uimm32</a><a class="headerlink" href="#uimm32" title="Permalink to this headline">¶</a></h3>
<p>A 32-bit <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.
The value must be in the range 0..0xFFFFFFFF.</p>
</div>
<div class="section" id="uimm20">
<span id="amdgpu-synid-uimm20"></span><h3><a class="toc-backref" href="#id27">uimm20</a><a class="headerlink" href="#uimm20" title="Permalink to this headline">¶</a></h3>
<p>A 20-bit <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
<p>The value must be in the range 0..0xFFFFF.</p>
</div>
<div class="section" id="simm21">
<span id="amdgpu-synid-simm21"></span><h3><a class="toc-backref" href="#id28">simm21</a><a class="headerlink" href="#simm21" title="Permalink to this headline">¶</a></h3>
<p>A 21-bit <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
<p>The value must be in the range -0x100000..0x0FFFFF.</p>
</div>
<div class="section" id="off">
<span id="amdgpu-synid-off"></span><h3><a class="toc-backref" href="#id29">off</a><a class="headerlink" href="#off" title="Permalink to this headline">¶</a></h3>
<p>A special entity which indicates that the value of this operand is not used.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 40%" />
<col style="width: 60%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>off</p></td>
<td><p>Indicates an unused operand.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
</div>
<div class="section" id="numbers">
<span id="amdgpu-synid-number"></span><h2><a class="toc-backref" href="#id30">Numbers</a><a class="headerlink" href="#numbers" title="Permalink to this headline">¶</a></h2>
<div class="section" id="integer-numbers">
<span id="amdgpu-synid-integer-number"></span><h3><a class="toc-backref" href="#id31">Integer Numbers</a><a class="headerlink" href="#integer-numbers" title="Permalink to this headline">¶</a></h3>
<p>Integer numbers are 64 bits wide.
They are converted to <a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a>
as described <a class="reference internal" href="#amdgpu-synid-int-conv"><span class="std std-ref">here</span></a>.</p>
<p>Integer numbers may be specified in binary, octal, hexadecimal and decimal formats:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 24%" />
<col style="width: 61%" />
<col style="width: 16%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Format</p></th>
<th class="head"><p>Syntax</p></th>
<th class="head"><p>Example</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>Decimal</p></td>
<td><p>[-]?[1-9][0-9]*</p></td>
<td><p>-1234</p></td>
</tr>
<tr class="row-odd"><td><p>Binary</p></td>
<td><p>[-]?0b[01]+</p></td>
<td><p>0b1010</p></td>
</tr>
<tr class="row-even"><td><p>Octal</p></td>
<td><p>[-]?0[0-7]+</p></td>
<td><p>010</p></td>
</tr>
<tr class="row-odd"><td><p>Hexadecimal</p></td>
<td><p>[-]?0x[0-9a-fA-F]+</p></td>
<td><p>0xff</p></td>
</tr>
<tr class="row-even"><td><p></p></td>
<td><p>[-]?[0x]?[0-9][0-9a-fA-F]*[hH]</p></td>
<td><p>0ffh</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="floating-point-numbers">
<span id="amdgpu-synid-floating-point-number"></span><h3><a class="toc-backref" href="#id32">Floating-Point Numbers</a><a class="headerlink" href="#floating-point-numbers" title="Permalink to this headline">¶</a></h3>
<p>All floating-point numbers are handled as double (64 bits wide).
They are converted to
<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a>
as described <a class="reference internal" href="#amdgpu-synid-fp-conv"><span class="std std-ref">here</span></a>.</p>
<p>Floating-point numbers may be specified in hexadecimal and decimal formats:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 11%" />
<col style="width: 51%" />
<col style="width: 20%" />
<col style="width: 18%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Format</p></th>
<th class="head"><p>Syntax</p></th>
<th class="head"><p>Examples</p></th>
<th class="head"><p>Note</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>Decimal</p></td>
<td><p>[-]?[0-9]*[.][0-9]*([eE][+-]?[0-9]*)?</p></td>
<td><p>-1.234, 234e2</p></td>
<td><p>Must include either
a decimal separator
or an exponent.</p></td>
</tr>
<tr class="row-odd"><td><p>Hexadecimal</p></td>
<td><p>[-]0x[0-9a-fA-F]*(.[0-9a-fA-F]*)?[pP][+-]?[0-9a-fA-F]+</p></td>
<td><p>-0x1afp-10, 0x.1afp10</p></td>
<td></td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
</div>
<div class="section" id="expressions">
<span id="amdgpu-synid-expression"></span><h2><a class="toc-backref" href="#id33">Expressions</a><a class="headerlink" href="#expressions" title="Permalink to this headline">¶</a></h2>
<p>An expression is evaluated to a 64-bit integer.
Note that floating-point expressions are not supported.</p>
<p>There are two kinds of expressions:</p>
<ul class="simple">
<li><p><a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">Absolute</span></a>.</p></li>
<li><p><a class="reference internal" href="#amdgpu-synid-relocatable-expression"><span class="std std-ref">Relocatable</span></a>.</p></li>
</ul>
<div class="section" id="absolute-expressions">
<span id="amdgpu-synid-absolute-expression"></span><h3><a class="toc-backref" href="#id34">Absolute Expressions</a><a class="headerlink" href="#absolute-expressions" title="Permalink to this headline">¶</a></h3>
<p>The value of an absolute expression does not change after program relocation.
Absolute expressions must not include unassigned and relocatable values
such as labels.</p>
<p>Absolute expressions are evaluated to 64-bit integer values and converted to
<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a>
as described <a class="reference internal" href="#amdgpu-synid-int-conv"><span class="std std-ref">here</span></a>.</p>
<p>Examples:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">x</span> <span class="o">=</span> <span class="o">-</span><span class="mi">1</span>
<span class="n">y</span> <span class="o">=</span> <span class="n">x</span> <span class="o">+</span> <span class="mi">10</span>
</pre></div>
</div>
</div>
<div class="section" id="relocatable-expressions">
<span id="amdgpu-synid-relocatable-expression"></span><h3><a class="toc-backref" href="#id35">Relocatable Expressions</a><a class="headerlink" href="#relocatable-expressions" title="Permalink to this headline">¶</a></h3>
<p>The value of a relocatable expression depends on program relocation.</p>
<p>Note that use of relocatable expressions is limited with branch targets
and 32-bit integer operands.</p>
<p>A relocatable expression is evaluated to a 64-bit integer value
which depends on operand kind and <a class="reference internal" href="AMDGPUUsage.html#amdgpu-relocation-records"><span class="std std-ref">relocation type</span></a>
of symbol(s) used in the expression. For example, if an instruction refers a label,
this reference is evaluated to an offset from the address after the instruction
to the label address:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">label</span><span class="p">:</span>
<span class="n">v_add_co_u32_e32</span> <span class="n">v0</span><span class="p">,</span> <span class="n">vcc</span><span class="p">,</span> <span class="n">label</span><span class="p">,</span> <span class="n">v1</span> <span class="o">//</span> <span class="s1">'label'</span> <span class="n">operand</span> <span class="ow">is</span> <span class="n">evaluated</span> <span class="n">to</span> <span class="o">-</span><span class="mi">4</span>
</pre></div>
</div>
<p>Note that values of relocatable expressions are usually unknown at assembly time;
they are resolved later by a linker and converted to
<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a>
as described <a class="reference internal" href="#amdgpu-synid-rl-conv"><span class="std std-ref">here</span></a>.</p>
</div>
<div class="section" id="operands-and-operations">
<h3><a class="toc-backref" href="#id36">Operands and Operations</a><a class="headerlink" href="#operands-and-operations" title="Permalink to this headline">¶</a></h3>
<p>Expressions are composed of 64-bit integer operands and operations.
Operands include <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>
and <a class="reference internal" href="#amdgpu-synid-symbol"><span class="std std-ref">symbols</span></a>.</p>
<p>Expressions may also use “.” which is a reference to the current PC (program counter).</p>
<p><a class="reference internal" href="#amdgpu-synid-expression-un-op"><span class="std std-ref">Unary</span></a> and <a class="reference internal" href="#amdgpu-synid-expression-bin-op"><span class="std std-ref">binary</span></a>
operations produce 64-bit integer results.</p>
</div>
<div class="section" id="syntax-of-expressions">
<h3><a class="toc-backref" href="#id37">Syntax of Expressions</a><a class="headerlink" href="#syntax-of-expressions" title="Permalink to this headline">¶</a></h3>
<p>Syntax of expressions is shown below:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">expr</span> <span class="p">:</span><span class="o">:=</span> <span class="n">expr</span> <span class="n">binop</span> <span class="n">expr</span> <span class="o">|</span> <span class="n">primaryexpr</span> <span class="p">;</span>
<span class="n">primaryexpr</span> <span class="p">:</span><span class="o">:=</span> <span class="s1">'('</span> <span class="n">expr</span> <span class="s1">')'</span> <span class="o">|</span> <span class="n">symbol</span> <span class="o">|</span> <span class="n">number</span> <span class="o">|</span> <span class="s1">'.'</span> <span class="o">|</span> <span class="n">unop</span> <span class="n">primaryexpr</span> <span class="p">;</span>
<span class="n">binop</span> <span class="p">:</span><span class="o">:=</span> <span class="s1">'&&'</span>
<span class="o">|</span> <span class="s1">'||'</span>
<span class="o">|</span> <span class="s1">'|'</span>
<span class="o">|</span> <span class="s1">'^'</span>
<span class="o">|</span> <span class="s1">'&'</span>
<span class="o">|</span> <span class="s1">'!'</span>
<span class="o">|</span> <span class="s1">'=='</span>
<span class="o">|</span> <span class="s1">'!='</span>
<span class="o">|</span> <span class="s1">'<>'</span>
<span class="o">|</span> <span class="s1">'<'</span>
<span class="o">|</span> <span class="s1">'<='</span>
<span class="o">|</span> <span class="s1">'>'</span>
<span class="o">|</span> <span class="s1">'>='</span>
<span class="o">|</span> <span class="s1">'<<'</span>
<span class="o">|</span> <span class="s1">'>>'</span>
<span class="o">|</span> <span class="s1">'+'</span>
<span class="o">|</span> <span class="s1">'-'</span>
<span class="o">|</span> <span class="s1">'*'</span>
<span class="o">|</span> <span class="s1">'/'</span>
<span class="o">|</span> <span class="s1">'%'</span> <span class="p">;</span>
<span class="n">unop</span> <span class="p">:</span><span class="o">:=</span> <span class="s1">'~'</span>
<span class="o">|</span> <span class="s1">'+'</span>
<span class="o">|</span> <span class="s1">'-'</span>
<span class="o">|</span> <span class="s1">'!'</span> <span class="p">;</span>
</pre></div>
</div>
</div>
<div class="section" id="binary-operators">
<span id="amdgpu-synid-expression-bin-op"></span><h3><a class="toc-backref" href="#id38">Binary Operators</a><a class="headerlink" href="#binary-operators" title="Permalink to this headline">¶</a></h3>
<p>Binary operators are described in the following table.
They operate on and produce 64-bit integers.
Operators with higher priority are performed first.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 15%" />
<col style="width: 14%" />
<col style="width: 71%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Operator</p></th>
<th class="head"><p>Priority</p></th>
<th class="head"><p>Meaning</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>*</p></td>
<td><p>5</p></td>
<td><p>Integer multiplication.</p></td>
</tr>
<tr class="row-odd"><td><p>/</p></td>
<td><p>5</p></td>
<td><p>Integer division.</p></td>
</tr>
<tr class="row-even"><td><p>%</p></td>
<td><p>5</p></td>
<td><p>Integer signed remainder.</p></td>
</tr>
<tr class="row-odd"><td><p>+</p></td>
<td><p>4</p></td>
<td><p>Integer addition.</p></td>
</tr>
<tr class="row-even"><td><p>-</p></td>
<td><p>4</p></td>
<td><p>Integer subtraction.</p></td>
</tr>
<tr class="row-odd"><td><p><<</p></td>
<td><p>3</p></td>
<td><p>Integer shift left.</p></td>
</tr>
<tr class="row-even"><td><p>>></p></td>
<td><p>3</p></td>
<td><p>Logical shift right.</p></td>
</tr>
<tr class="row-odd"><td><p>==</p></td>
<td><p>2</p></td>
<td><p>Equality comparison.</p></td>
</tr>
<tr class="row-even"><td><p>!=</p></td>
<td><p>2</p></td>
<td><p>Inequality comparison.</p></td>
</tr>
<tr class="row-odd"><td><p><></p></td>
<td><p>2</p></td>
<td><p>Inequality comparison.</p></td>
</tr>
<tr class="row-even"><td><p><</p></td>
<td><p>2</p></td>
<td><p>Signed less than comparison.</p></td>
</tr>
<tr class="row-odd"><td><p><=</p></td>
<td><p>2</p></td>
<td><p>Signed less than or equal comparison.</p></td>
</tr>
<tr class="row-even"><td><p>></p></td>
<td><p>2</p></td>
<td><p>Signed greater than comparison.</p></td>
</tr>
<tr class="row-odd"><td><p>>=</p></td>
<td><p>2</p></td>
<td><p>Signed greater than or equal comparison.</p></td>
</tr>
<tr class="row-even"><td><p>|</p></td>
<td><p>1</p></td>
<td><p>Bitwise or.</p></td>
</tr>
<tr class="row-odd"><td><p>^</p></td>
<td><p>1</p></td>
<td><p>Bitwise xor.</p></td>
</tr>
<tr class="row-even"><td><p>&</p></td>
<td><p>1</p></td>
<td><p>Bitwise and.</p></td>
</tr>
<tr class="row-odd"><td><p>&&</p></td>
<td><p>0</p></td>
<td><p>Logical and.</p></td>
</tr>
<tr class="row-even"><td><p>||</p></td>
<td><p>0</p></td>
<td><p>Logical or.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="unary-operators">
<span id="amdgpu-synid-expression-un-op"></span><h3><a class="toc-backref" href="#id39">Unary Operators</a><a class="headerlink" href="#unary-operators" title="Permalink to this headline">¶</a></h3>
<p>Unary operators are described in the following table.
They operate on and produce 64-bit integers.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 18%" />
<col style="width: 82%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Operator</p></th>
<th class="head"><p>Meaning</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>!</p></td>
<td><p>Logical negation.</p></td>
</tr>
<tr class="row-odd"><td><p>~</p></td>
<td><p>Bitwise negation.</p></td>
</tr>
<tr class="row-even"><td><p>+</p></td>
<td><p>Integer unary plus.</p></td>
</tr>
<tr class="row-odd"><td><p>-</p></td>
<td><p>Integer unary minus.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="symbols">
<span id="amdgpu-synid-symbol"></span><h3><a class="toc-backref" href="#id40">Symbols</a><a class="headerlink" href="#symbols" title="Permalink to this headline">¶</a></h3>
<p>A symbol is a named 64-bit integer value, representing a relocatable
address or an absolute (non-relocatable) number.</p>
<dl class="simple">
<dt>Symbol names have the following syntax:</dt><dd><p><code class="docutils literal notranslate"><span class="pre">[a-zA-Z_.][a-zA-Z0-9_$.@]*</span></code></p>
</dd>
</dl>
<p>The table below provides several examples of syntax used for symbol definition.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 22%" />
<col style="width: 78%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Meaning</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>.globl <S></p></td>
<td><p>Declares a global symbol S without assigning it a value.</p></td>
</tr>
<tr class="row-odd"><td><p>.set <S>, <E></p></td>
<td><p>Assigns the value of an expression E to a symbol S.</p></td>
</tr>
<tr class="row-even"><td><p><S> = <E></p></td>
<td><p>Assigns the value of an expression E to a symbol S.</p></td>
</tr>
<tr class="row-odd"><td><p><S>:</p></td>
<td><p>Declares a label S and assigns it the current PC value.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>A symbol may be used before it is declared or assigned;
unassigned symbols are assumed to be PC-relative.</p>
<p>Additional information about symbols may be found <a class="reference internal" href="AMDGPUUsage.html#amdgpu-symbols"><span class="std std-ref">here</span></a>.</p>
</div>
</div>
<div class="section" id="type-and-size-conversion">
<span id="amdgpu-synid-conv"></span><h2><a class="toc-backref" href="#id41">Type and Size Conversion</a><a class="headerlink" href="#type-and-size-conversion" title="Permalink to this headline">¶</a></h2>
<p>This section describes what happens when a 64-bit
<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>, a
<a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point number</span></a> or an
<a class="reference internal" href="#amdgpu-synid-expression"><span class="std std-ref">expression</span></a>
is used for an operand which has a different type or size.</p>
<div class="section" id="conversion-of-integer-values">
<span id="amdgpu-synid-int-conv"></span><h3><a class="toc-backref" href="#id42">Conversion of Integer Values</a><a class="headerlink" href="#conversion-of-integer-values" title="Permalink to this headline">¶</a></h3>
<p>Instruction operands may be specified as 64-bit <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a> or
<a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>. These values are converted to
the <a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a> using the following steps:</p>
<p>1. <em>Validation</em>. Assembler checks if the input value may be truncated without loss to the required <em>truncation width</em>
(see the table below). There are two cases when this operation is enabled:</p>
<blockquote>
<div><ul class="simple">
<li><p>The truncated bits are all 0.</p></li>
<li><p>The truncated bits are all 1 and the value after truncation has its MSB bit set.</p></li>
</ul>
</div></blockquote>
<p>In all other cases assembler triggers an error.</p>
<p>2. <em>Conversion</em>. The input value is converted to the expected type as described in the table below.
Depending on operand kind, this conversion is performed by either assembler or AMDGPU H/W (or both).</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 12%" />
<col style="width: 15%" />
<col style="width: 13%" />
<col style="width: 60%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Expected type</p></th>
<th class="head"><p>Truncation Width</p></th>
<th class="head"><p>Conversion</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>i16, u16, b16</p></td>
<td><p>16</p></td>
<td><p>num.u16</p></td>
<td><p>Truncate to 16 bits.</p></td>
</tr>
<tr class="row-odd"><td><p>i32, u32, b32</p></td>
<td><p>32</p></td>
<td><p>num.u32</p></td>
<td><p>Truncate to 32 bits.</p></td>
</tr>
<tr class="row-even"><td><p>i64</p></td>
<td><p>32</p></td>
<td><p>{-1,num.i32}</p></td>
<td><p>Truncate to 32 bits and then sign-extend the result to 64 bits.</p></td>
</tr>
<tr class="row-odd"><td><p>u64, b64</p></td>
<td><p>32</p></td>
<td><p>{0,num.u32}</p></td>
<td><p>Truncate to 32 bits and then zero-extend the result to 64 bits.</p></td>
</tr>
<tr class="row-even"><td><p>f16</p></td>
<td><p>16</p></td>
<td><p>num.u16</p></td>
<td><p>Use low 16 bits as an f16 value.</p></td>
</tr>
<tr class="row-odd"><td><p>f32</p></td>
<td><p>32</p></td>
<td><p>num.u32</p></td>
<td><p>Use low 32 bits as an f32 value.</p></td>
</tr>
<tr class="row-even"><td><p>f64</p></td>
<td><p>32</p></td>
<td><p>{num.u32,0}</p></td>
<td><p>Use low 32 bits of the number as high 32 bits
of the result; low 32 bits of the result are zeroed.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Examples of enabled conversions:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">1</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0xFFFF</span>
<span class="n">v_add_f16</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">1</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0xFFFF</span> <span class="p">(</span><span class="n">NaN</span><span class="p">)</span>
<span class="o">//</span>
<span class="n">v_add_u32</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">1</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0xFFFFFFFF</span>
<span class="n">v_add_f32</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">1</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0xFFFFFFFF</span> <span class="p">(</span><span class="n">NaN</span><span class="p">)</span>
<span class="o">//</span>
<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mh">0xff00</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0xff00</span>
<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mh">0xffffffffffffff00</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0xff00</span>
<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">256</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0xff00</span>
<span class="o">//</span>
<span class="n">s_bfe_i64</span> <span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mh">0xffefffff</span><span class="p">,</span> <span class="n">s3</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0xffffffffffefffff</span>
<span class="n">s_bfe_u64</span> <span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mh">0xffefffff</span><span class="p">,</span> <span class="n">s3</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0x00000000ffefffff</span>
<span class="n">v_ceil_f64_e32</span> <span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mh">0xffefffff</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0xffefffff00000000</span> <span class="p">(</span><span class="o">-</span><span class="mf">1.7976922776554302e308</span><span class="p">)</span>
<span class="o">//</span>
<span class="n">x</span> <span class="o">=</span> <span class="mh">0xffefffff</span> <span class="o">//</span>
<span class="n">s_bfe_i64</span> <span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="n">x</span><span class="p">,</span> <span class="n">s3</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0xffffffffffefffff</span>
<span class="n">s_bfe_u64</span> <span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="n">x</span><span class="p">,</span> <span class="n">s3</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0x00000000ffefffff</span>
<span class="n">v_ceil_f64_e32</span> <span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="n">x</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0xffefffff00000000</span> <span class="p">(</span><span class="o">-</span><span class="mf">1.7976922776554302e308</span><span class="p">)</span>
</pre></div>
</div>
<p>Examples of disabled conversions:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mh">0x1ff00</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="n">truncated</span> <span class="n">bits</span> <span class="n">are</span> <span class="ow">not</span> <span class="nb">all</span> <span class="mi">0</span> <span class="ow">or</span> <span class="mi">1</span>
<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mh">0xffffffffffff00ff</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="n">truncated</span> <span class="n">bits</span> <span class="n">do</span> <span class="ow">not</span> <span class="n">match</span> <span class="n">MSB</span> <span class="n">of</span> <span class="n">the</span> <span class="n">result</span>
</pre></div>
</div>
</div>
<div class="section" id="conversion-of-floating-point-values">
<span id="amdgpu-synid-fp-conv"></span><h3><a class="toc-backref" href="#id43">Conversion of Floating-Point Values</a><a class="headerlink" href="#conversion-of-floating-point-values" title="Permalink to this headline">¶</a></h3>
<p>Instruction operands may be specified as 64-bit <a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a>.
These values are converted to the <a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a> using the following steps:</p>
<p>1. <em>Validation</em>. Assembler checks if the input f64 number can be converted
to the <em>required floating-point type</em> (see the table below) without overflow or underflow.
Precision lost is allowed. If this conversion is not possible, assembler triggers an error.</p>
<p>2. <em>Conversion</em>. The input value is converted to the expected type as described in the table below.
Depending on operand kind, this is performed by either assembler or AMDGPU H/W (or both).</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 13%" />
<col style="width: 14%" />
<col style="width: 15%" />
<col style="width: 58%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Expected type</p></th>
<th class="head"><p>Required FP Type</p></th>
<th class="head"><p>Conversion</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>i16, u16, b16</p></td>
<td><p>f16</p></td>
<td><p>f16(num)</p></td>
<td><p>Convert to f16 and use bits of the result as an integer value.
The value has to be encoded as a literal or an error occurs.
Note that the value cannot be encoded as an inline constant.</p></td>
</tr>
<tr class="row-odd"><td><p>i32, u32, b32</p></td>
<td><p>f32</p></td>
<td><p>f32(num)</p></td>
<td><p>Convert to f32 and use bits of the result as an integer value.</p></td>
</tr>
<tr class="row-even"><td><p>i64, u64, b64</p></td>
<td><p>-</p></td>
<td><p>-</p></td>
<td><p>Conversion disabled.</p></td>
</tr>
<tr class="row-odd"><td><p>f16</p></td>
<td><p>f16</p></td>
<td><p>f16(num)</p></td>
<td><p>Convert to f16.</p></td>
</tr>
<tr class="row-even"><td><p>f32</p></td>
<td><p>f32</p></td>
<td><p>f32(num)</p></td>
<td><p>Convert to f32.</p></td>
</tr>
<tr class="row-odd"><td><p>f64</p></td>
<td><p>f64</p></td>
<td><p>{num.u32.hi,0}</p></td>
<td><p>Use high 32 bits of the number as high 32 bits of the result;
zero-fill low 32 bits of the result.</p>
<p>Note that the result may differ from the original number.</p>
</td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Examples of enabled conversions:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
<span class="n">v_add_f16</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">1.0</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0x3C00</span> <span class="p">(</span><span class="mf">1.0</span><span class="p">)</span>
<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">1.0</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0x3C00</span>
<span class="o">//</span>
<span class="n">v_add_f32</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">1.0</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0x3F800000</span> <span class="p">(</span><span class="mf">1.0</span><span class="p">)</span>
<span class="n">v_add_u32</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">1.0</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">src0</span> <span class="o">=</span> <span class="mh">0x3F800000</span>
<span class="o">//</span> <span class="n">src0</span> <span class="n">before</span> <span class="n">conversion</span><span class="p">:</span>
<span class="o">//</span> <span class="mf">1.7976931348623157e308</span> <span class="o">=</span> <span class="mh">0x7fefffffffffffff</span>
<span class="o">//</span> <span class="n">src0</span> <span class="n">after</span> <span class="n">conversion</span><span class="p">:</span>
<span class="o">//</span> <span class="mf">1.7976922776554302e308</span> <span class="o">=</span> <span class="mh">0x7fefffff00000000</span>
<span class="n">v_ceil_f64</span> <span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mf">1.7976931348623157e308</span>
<span class="n">v_add_f16</span> <span class="n">v1</span><span class="p">,</span> <span class="mf">65500.0</span><span class="p">,</span> <span class="n">v2</span> <span class="o">//</span> <span class="n">ok</span> <span class="k">for</span> <span class="n">f16</span><span class="o">.</span>
<span class="n">v_add_f32</span> <span class="n">v1</span><span class="p">,</span> <span class="mf">65600.0</span><span class="p">,</span> <span class="n">v2</span> <span class="o">//</span> <span class="n">ok</span> <span class="k">for</span> <span class="n">f32</span><span class="p">,</span> <span class="n">but</span> <span class="n">would</span> <span class="n">result</span> <span class="ow">in</span> <span class="n">overflow</span> <span class="k">for</span> <span class="n">f16</span><span class="o">.</span>
</pre></div>
</div>
<p>Examples of disabled conversions:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
<span class="n">v_add_f16</span> <span class="n">v1</span><span class="p">,</span> <span class="mf">65600.0</span><span class="p">,</span> <span class="n">v2</span> <span class="o">//</span> <span class="n">overflow</span>
</pre></div>
</div>
</div>
<div class="section" id="conversion-of-relocatable-values">
<span id="amdgpu-synid-rl-conv"></span><h3><a class="toc-backref" href="#id44">Conversion of Relocatable Values</a><a class="headerlink" href="#conversion-of-relocatable-values" title="Permalink to this headline">¶</a></h3>
<p><a class="reference internal" href="#amdgpu-synid-relocatable-expression"><span class="std std-ref">Relocatable expressions</span></a>
may be used with 32-bit integer operands and jump targets.</p>
<p>When the value of a relocatable expression is resolved by a linker, it is
converted as needed and truncated to the operand size. The conversion depends
on <a class="reference internal" href="AMDGPUUsage.html#amdgpu-relocation-records"><span class="std std-ref">relocation type</span></a> and operand kind.</p>
<p>For example, when a 32-bit operand of an instruction refers a relocatable expression <em>expr</em>,
this reference is evaluated to a 64-bit offset from the address after the
instruction to the address being referenced, <em>counted in bytes</em>.
Then the value is truncated to 32 bits and encoded as a literal:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">expr</span> <span class="o">=</span> <span class="o">.</span>
<span class="n">v_add_co_u32_e32</span> <span class="n">v0</span><span class="p">,</span> <span class="n">vcc</span><span class="p">,</span> <span class="n">expr</span><span class="p">,</span> <span class="n">v1</span> <span class="o">//</span> <span class="s1">'expr'</span> <span class="n">operand</span> <span class="ow">is</span> <span class="n">evaluated</span> <span class="n">to</span> <span class="o">-</span><span class="mi">4</span>
<span class="o">//</span> <span class="ow">and</span> <span class="n">then</span> <span class="n">truncated</span> <span class="n">to</span> <span class="mh">0xFFFFFFFC</span>
</pre></div>
</div>
<p>As another example, when a branch instruction refers a label,
this reference is evaluated to an offset from the address after the
instruction to the label address, <em>counted in dwords</em>.
Then the value is truncated to 16 bits:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">label</span><span class="p">:</span>
<span class="n">s_branch</span> <span class="n">label</span> <span class="o">//</span> <span class="s1">'label'</span> <span class="n">operand</span> <span class="ow">is</span> <span class="n">evaluated</span> <span class="n">to</span> <span class="o">-</span><span class="mi">1</span> <span class="ow">and</span> <span class="n">truncated</span> <span class="n">to</span> <span class="mh">0xFFFF</span>
</pre></div>
</div>
</div>
</div>
</div>
<div class="clearer"></div>
</div>
</div>
</div>
<div class="clearer"></div>
</div>
<div class="related" role="navigation" aria-label="related navigation">
<h3>Navigation</h3>
<ul>
<li class="right" style="margin-right: 10px">
<a href="genindex.html" title="General Index"
>index</a></li>
<li class="right" >
<a href="AMDGPUInstructionSyntax.html" title="AMDGPU Instruction Syntax"
>next</a> |</li>
<li class="right" >
<a href="AMDGPUModifierSyntax.html" title="Syntax of AMDGPU Instruction Modifiers"
>previous</a> |</li>
<li><a href="https://llvm.org/">LLVM Home</a> | </li>
<li><a href="index.html">Documentation</a>»</li>
<li class="nav-item nav-item-1"><a href="UserGuides.html" >User Guides</a> »</li>
<li class="nav-item nav-item-2"><a href="AMDGPUUsage.html" >User Guide for AMDGPU Backend</a> »</li>
<li class="nav-item nav-item-this"><a href="">Syntax of AMDGPU Instruction Operands</a></li>
</ul>
</div>
<div class="footer" role="contentinfo">
© Copyright 2003-2021, LLVM Project.
Last updated on 2021-09-18.
Created using <a href="https://www.sphinx-doc.org/">Sphinx</a> 3.5.4.
</div>
</body>
</html>
|
