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<div class="section" id="vector-predication-roadmap">
<h1>Vector Predication Roadmap<a class="headerlink" href="#vector-predication-roadmap" title="Permalink to this headline">¶</a></h1>
<div class="contents local topic" id="table-of-contents">
<p class="topic-title">Table of Contents</p>
<ul class="simple">
<li><p><a class="reference internal" href="#motivation" id="id3">Motivation</a></p></li>
<li><p><a class="reference internal" href="#roadmap" id="id4">Roadmap</a></p>
<ul>
<li><p><a class="reference internal" href="#ir-level-vp-intrinsics" id="id5">1. IR-level VP intrinsics</a></p></li>
<li><p><a class="reference internal" href="#codegen-support" id="id6">2. CodeGen support</a></p></li>
<li><p><a class="reference internal" href="#lift-instsimplify-instcombine-dagcombiner-to-vp" id="id7">3. Lift InstSimplify/InstCombine/DAGCombiner to VP</a></p></li>
<li><p><a class="reference internal" href="#deprecate-llvm-masked-llvm-experimental-reduce" id="id8">4. Deprecate llvm.masked.* / llvm.experimental.reduce.*</a></p></li>
<li><p><a class="reference internal" href="#predicated-ir-instructions" id="id9">5. Predicated IR Instructions</a></p></li>
</ul>
</li>
<li><p><a class="reference internal" href="#references" id="id10">References</a></p></li>
</ul>
</div>
<div class="section" id="motivation">
<h2><a class="toc-backref" href="#id3">Motivation</a><a class="headerlink" href="#motivation" title="Permalink to this headline">¶</a></h2>
<p>This proposal defines a roadmap towards native vector predication in LLVM,
specifically for vector instructions with a mask and/or an explicit vector
length. LLVM currently has no target-independent means to model predicated
vector instructions for modern SIMD ISAs such as AVX512, ARM SVE, the RISC-V V
extension and NEC SX-Aurora. Only some predicated vector operations, such as
masked loads and stores, are available through intrinsics <a class="reference internal" href="#maskedir" id="id1"><span>[MaskedIR]</span></a>.</p>
<p>The Vector Predication (VP) extensions is a concrete RFC and prototype
implementation to achieve native vector predication in LLVM. The VP prototype
and all related discussions can be found in the VP patch on Phabricator
<a class="reference internal" href="#vprfc" id="id2"><span>[VPRFC]</span></a>.</p>
</div>
<div class="section" id="roadmap">
<h2><a class="toc-backref" href="#id4">Roadmap</a><a class="headerlink" href="#roadmap" title="Permalink to this headline">¶</a></h2>
<div class="section" id="ir-level-vp-intrinsics">
<h3><a class="toc-backref" href="#id5">1. IR-level VP intrinsics</a><a class="headerlink" href="#ir-level-vp-intrinsics" title="Permalink to this headline">¶</a></h3>
<ul class="simple">
<li><p>There is a consensus on the semantics/instruction set of VP.</p></li>
<li><p>VP intrinsics and attributes are available on IR level.</p></li>
<li><p>TTI has capability flags for VP (<code class="docutils literal notranslate"><span class="pre">supportsVP()</span></code>?,
<code class="docutils literal notranslate"><span class="pre">haveActiveVectorLength()</span></code>?).</p></li>
</ul>
<p>Result: VP usable for IR-level vectorizers (LV, VPlan, RegionVectorizer),
potential integration in Clang with builtins.</p>
</div>
<div class="section" id="codegen-support">
<h3><a class="toc-backref" href="#id6">2. CodeGen support</a><a class="headerlink" href="#codegen-support" title="Permalink to this headline">¶</a></h3>
<ul class="simple">
<li><p>VP intrinsics translate to first-class SDNodes
(eg <code class="docutils literal notranslate"><span class="pre">llvm.vp.fdiv.*</span> <span class="pre">-></span> <span class="pre">vp_fdiv</span></code>).</p></li>
<li><p>VP legalization (legalize explicit vector length to mask (AVX512), legalize VP
SDNodes to pre-existing ones (SSE, NEON)).</p></li>
</ul>
<p>Result: Backend development based on VP SDNodes.</p>
</div>
<div class="section" id="lift-instsimplify-instcombine-dagcombiner-to-vp">
<h3><a class="toc-backref" href="#id7">3. Lift InstSimplify/InstCombine/DAGCombiner to VP</a><a class="headerlink" href="#lift-instsimplify-instcombine-dagcombiner-to-vp" title="Permalink to this headline">¶</a></h3>
<ul class="simple">
<li><p>Introduce PredicatedInstruction, PredicatedBinaryOperator, .. helper classes
that match standard vector IR and VP intrinsics.</p></li>
<li><p>Add a matcher context to PatternMatch and context-aware IR Builder APIs.</p></li>
<li><p>Incrementally lift DAGCombiner to work on VP SDNodes as well as on regular
vector instructions.</p></li>
<li><p>Incrementally lift InstCombine/InstSimplify to operate on VP as well as
regular IR instructions.</p></li>
</ul>
<p>Result: Optimization of VP intrinsics on par with standard vector instructions.</p>
</div>
<div class="section" id="deprecate-llvm-masked-llvm-experimental-reduce">
<h3><a class="toc-backref" href="#id8">4. Deprecate llvm.masked.* / llvm.experimental.reduce.*</a><a class="headerlink" href="#deprecate-llvm-masked-llvm-experimental-reduce" title="Permalink to this headline">¶</a></h3>
<ul class="simple">
<li><p>Modernize llvm.masked.* / llvm.experimental.reduce* by translating to VP.</p></li>
<li><p>DCE transitional APIs.</p></li>
</ul>
<p>Result: VP has superseded earlier vector intrinsics.</p>
</div>
<div class="section" id="predicated-ir-instructions">
<h3><a class="toc-backref" href="#id9">5. Predicated IR Instructions</a><a class="headerlink" href="#predicated-ir-instructions" title="Permalink to this headline">¶</a></h3>
<ul class="simple">
<li><p>Vector instructions have an optional mask and vector length parameter. These
lower to VP SDNodes (from Stage 2).</p></li>
<li><p>Phase out VP intrinsics, only keeping those that are not equivalent to
vectorized scalar instructions (reduce, shuffles, ..)</p></li>
<li><p>InstCombine/InstSimplify expect predication in regular Instructions (Stage (3)
has laid the groundwork).</p></li>
</ul>
<p>Result: Native vector predication in IR.</p>
</div>
</div>
<div class="section" id="references">
<h2><a class="toc-backref" href="#id10">References</a><a class="headerlink" href="#references" title="Permalink to this headline">¶</a></h2>
<dl class="citation">
<dt class="label" id="maskedir"><span class="brackets"><a class="fn-backref" href="#id1">MaskedIR</a></span></dt>
<dd><p><cite>llvm.masked.*</cite> intrinsics,
<a class="reference external" href="https://llvm.org/docs/LangRef.html#masked-vector-load-and-store-intrinsics">https://llvm.org/docs/LangRef.html#masked-vector-load-and-store-intrinsics</a></p>
</dd>
<dt class="label" id="vprfc"><span class="brackets"><a class="fn-backref" href="#id2">VPRFC</a></span></dt>
<dd><p>RFC: Prototype & Roadmap for vector predication in LLVM,
<a class="reference external" href="https://reviews.llvm.org/D57504">https://reviews.llvm.org/D57504</a></p>
</dd>
</dl>
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