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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64IB
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64IBE
declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
define signext i32 @bcompress32(i32 signext %a, i32 signext %b) nounwind {
; RV64IB-LABEL: bcompress32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: bcompressw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBE-LABEL: bcompress32:
; RV64IBE: # %bb.0:
; RV64IBE-NEXT: bcompressw a0, a0, a1
; RV64IBE-NEXT: ret
%tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
ret i32 %tmp
}
define signext i32 @bcompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64IB-LABEL: bcompress32_demandedbits:
; RV64IB: # %bb.0:
; RV64IB-NEXT: add a0, a0, a1
; RV64IB-NEXT: add a1, a2, a3
; RV64IB-NEXT: bcompressw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBE-LABEL: bcompress32_demandedbits:
; RV64IBE: # %bb.0:
; RV64IBE-NEXT: add a0, a0, a1
; RV64IBE-NEXT: add a1, a2, a3
; RV64IBE-NEXT: bcompressw a0, a0, a1
; RV64IBE-NEXT: ret
%e = add i32 %a, %b
%f = add i32 %c, %d
%tmp = call i32 @llvm.riscv.bcompress.i32(i32 %e, i32 %f)
ret i32 %tmp
}
declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
define signext i32 @bdecompress32(i32 signext %a, i32 signext %b) nounwind {
; RV64IB-LABEL: bdecompress32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: bdecompressw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBE-LABEL: bdecompress32:
; RV64IBE: # %bb.0:
; RV64IBE-NEXT: bdecompressw a0, a0, a1
; RV64IBE-NEXT: ret
%tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
ret i32 %tmp
}
define signext i32 @bdecompress32_demandedbits(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64IB-LABEL: bdecompress32_demandedbits:
; RV64IB: # %bb.0:
; RV64IB-NEXT: add a0, a0, a1
; RV64IB-NEXT: add a1, a2, a3
; RV64IB-NEXT: bdecompressw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBE-LABEL: bdecompress32_demandedbits:
; RV64IBE: # %bb.0:
; RV64IBE-NEXT: add a0, a0, a1
; RV64IBE-NEXT: add a1, a2, a3
; RV64IBE-NEXT: bdecompressw a0, a0, a1
; RV64IBE-NEXT: ret
%e = add i32 %a, %b
%f = add i32 %c, %d
%tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %e, i32 %f)
ret i32 %tmp
}
declare i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
define i64 @bcompress64(i64 %a, i64 %b) nounwind {
; RV64IB-LABEL: bcompress64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: bcompress a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBE-LABEL: bcompress64:
; RV64IBE: # %bb.0:
; RV64IBE-NEXT: bcompress a0, a0, a1
; RV64IBE-NEXT: ret
%tmp = call i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
ret i64 %tmp
}
declare i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
define i64 @bdecompress64(i64 %a, i64 %b) nounwind {
; RV64IB-LABEL: bdecompress64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: bdecompress a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBE-LABEL: bdecompress64:
; RV64IBE: # %bb.0:
; RV64IBE-NEXT: bdecompress a0, a0, a1
; RV64IBE-NEXT: ret
%tmp = call i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
ret i64 %tmp
}
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