File: A55-6-mul.s

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llvm-toolchain-13 1%3A13.0.1-6~deb11u1
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-views=false --summary-view --iterations=1000 < %s | FileCheck %s

# It appears that ADD and MUL fuse together, if both can be issued in
# one cycle:
#
#     add  w12, w8, #1
#     mul  w10, w12, w10
#
# FIXME: MCA (and LLVM scheduling model) do not support this. The test
# case uses different registers to break the pattern.

add	w8, w8, #1
add	w13, w8, #1
mul	w10, w12, w10

# CHECK:      Iterations:        1000
# CHECK-NEXT: Instructions:      3000
# CHECK-NEXT: Total Cycles:      3003
# CHECK-NEXT: Total uOps:        3000

# CHECK:      Dispatch Width:    2
# CHECK-NEXT: uOps Per Cycle:    1.00
# CHECK-NEXT: IPC:               1.00
# CHECK-NEXT: Block RThroughput: 1.5