1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
|
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=SIZE %s
; END.
define amdgpu_kernel void @fneg_f32() {
; CHECK-LABEL: 'fneg_f32'
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f32 = fneg float undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f32 = fneg <2 x float> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f32 = fneg <3 x float> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f32 = fneg <4 x float> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f32 = fneg <5 x float> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v8f32 = fneg <8 x float> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v9f32 = fneg <9 x float> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; SIZE-LABEL: 'fneg_f32'
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f32 = fneg float undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f32 = fneg <2 x float> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f32 = fneg <3 x float> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f32 = fneg <4 x float> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f32 = fneg <5 x float> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v8f32 = fneg <8 x float> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v9f32 = fneg <9 x float> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%f32 = fneg float undef
%v2f32 = fneg <2 x float> undef
%v3f32 = fneg <3 x float> undef
%v4f32 = fneg <4 x float> undef
%v5f32 = fneg <5 x float> undef
%v8f32 = fneg <8 x float> undef
%v9f32 = fneg <9 x float> undef
ret void
}
define amdgpu_kernel void @fneg_f64() {
; CHECK-LABEL: 'fneg_f64'
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f64 = fneg double undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f64 = fneg <2 x double> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f64 = fneg <3 x double> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f64 = fneg <4 x double> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f64 = fneg <5 x double> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; SIZE-LABEL: 'fneg_f64'
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f64 = fneg double undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f64 = fneg <2 x double> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f64 = fneg <3 x double> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f64 = fneg <4 x double> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f64 = fneg <5 x double> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%f64 = fneg double undef
%v2f64 = fneg <2 x double> undef
%v3f64 = fneg <3 x double> undef
%v4f64 = fneg <4 x double> undef
%v5f64 = fneg <5 x double> undef
ret void
}
define amdgpu_kernel void @fneg_f16() {
; CHECK-LABEL: 'fneg_f16'
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f16 = fneg half undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f16 = fneg <2 x half> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f16 = fneg <3 x half> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f16 = fneg <4 x half> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f16 = fneg <5 x half> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v16f16 = fneg <16 x half> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v17f16 = fneg <17 x half> undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; SIZE-LABEL: 'fneg_f16'
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f16 = fneg half undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f16 = fneg <2 x half> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f16 = fneg <3 x half> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f16 = fneg <4 x half> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f16 = fneg <5 x half> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v16f16 = fneg <16 x half> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v17f16 = fneg <17 x half> undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%f16 = fneg half undef
%v2f16 = fneg <2 x half> undef
%v3f16 = fneg <3 x half> undef
%v4f16 = fneg <4 x half> undef
%v5f16 = fneg <5 x half> undef
%v16f16 = fneg <16 x half> undef
%v17f16 = fneg <17 x half> undef
ret void
}
define i32 @fneg_idiom(i32 %arg) {
; CHECK-LABEL: 'fneg_idiom'
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F32 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F32 = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = fsub double -0.000000e+00, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V4F64 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V8F64 = fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret i32 undef
;
; SIZE-LABEL: 'fneg_idiom'
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F32 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F32 = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = fsub double -0.000000e+00, undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4F64 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V8F64 = fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, undef
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
%F32 = fsub float -0.0, undef
%V4F32 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, undef
%V8F32 = fsub <8 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, undef
%V16F32 = fsub <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, undef
%F64 = fsub double -0.0, undef
%V2F64 = fsub <2 x double> <double -0.0, double -0.0>, undef
%V4F64 = fsub <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, undef
%V8F64 = fsub <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, undef
ret i32 undef
}
|
