File: select-neon-vcvtfxu2fp.mir

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llvm-toolchain-14 1%3A14.0.6-12
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -mattr=+neon,+fullfp16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

  define void @vcvtfxu2fp_s64_fpr() { ret void }
...

---
# Check that we select a 64-bit FPR vcvtfxu2fp intrinsic into UCVTFd for FPR64.
name:            vcvtfxu2fp_s64_fpr
legalized:       true
regBankSelected: true

registers:
  - { id: 0, class: fpr }
  - { id: 1, class: gpr }
  - { id: 2, class: fpr }

body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: vcvtfxu2fp_s64_fpr
    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK: [[UCVTFd:%[0-9]+]]:fpr64 = UCVTFd [[COPY]], 12
    ; CHECK: $d1 = COPY [[UCVTFd]]
    %0(s64) = COPY $d0
    %1(s32) = G_CONSTANT i32 12
    %2(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp.f64), %0, %1
    $d1 = COPY %2(s64)
...