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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o -| FileCheck %s
define <2 x i64> @test1(<4 x i32> %x) #0 {
; CHECK-LABEL: test1:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: mov w9, v0.s[2]
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov v0.d[1], x9
; CHECK-NEXT: ret
%i1 = extractelement <4 x i32> %x, i32 1
%zi1 = zext i32 %i1 to i64
%i2 = extractelement <4 x i32> %x, i32 2
%zi2 = zext i32 %i2 to i64
%v1 = insertelement <2 x i64> undef, i64 %zi1, i32 0
%v2 = insertelement <2 x i64> %v1, i64 %zi2, i32 1
ret <2 x i64> %v2
}
define <4 x i64> @test2(<4 x i32> %0) {
; CHECK-LABEL: test2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, .LCPI1_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: mov w9, v0.s[2]
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: mov v1.d[1], x9
; CHECK-NEXT: ret
entry:
%1 = add <4 x i32> %0, <i32 -4, i32 -8, i32 -12, i32 -16>
%2 = extractelement <4 x i32> %1, i32 1
%zext1 = zext i32 %2 to i64
%3 = extractelement <4 x i32> %1, i32 2
%zext2 = zext i32 %3 to i64
%4 = insertelement <4 x i64> undef, i64 %zext1, i32 2
%5 = insertelement <4 x i64> %4, i64 %zext2, i32 3
ret <4 x i64> %5
}
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