File: aarch64-ldst-subsuperReg-no-ldp.mir

package info (click to toggle)
llvm-toolchain-14 1%3A14.0.6-12
  • links: PTS, VCS
  • area: main
  • in suites: bookworm
  • size: 1,496,180 kB
  • sloc: cpp: 5,593,972; ansic: 986,872; asm: 585,869; python: 184,223; objc: 72,530; lisp: 31,119; f90: 27,793; javascript: 9,780; pascal: 9,762; sh: 9,482; perl: 7,468; ml: 5,432; awk: 3,523; makefile: 2,538; xml: 953; cs: 573; fortran: 567
file content (39 lines) | stat: -rw-r--r-- 1,118 bytes parent folder | download | duplicates (19) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
 
# RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -run-pass=aarch64-ldst-opt %s -o - | FileCheck %s
#
# The test below tests that when the AArch64 Load Store Optimization pass tries to
# convert load instructions into a ldp instruction, and when the destination
# registers are sub/super register of each other, then the convertion should not occur.
#
# For example, for the following pattern:
#     ldr x10 [x9]
#     ldr w10 [x9, 8],
# We cannot convert it to an ldp instruction.
#
# CHECK-NOT: LDP
# CHECK: $x10 = LDRSWui $x9, 0
# CHECK: $w10 = LDRWui $x9, 1
# CHECK: RET
---
name:            test1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x9
    $x10 = LDRSWui $x9, 0 :: (load (s32))
    $w10 = LDRWui $x9, 1 :: (load (s32))
    RET undef $lr, implicit undef $w0
...
# CHECK-NOT: LDP
# CHECK: $w10 = LDRWui $x9, 0
# CHECK: $x10 = LDRSWui $x9, 1
# CHECK: RET
---
name:            test2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x9
    $w10 = LDRWui $x9, 0 :: (load (s32))
    $x10 = LDRSWui $x9, 1 :: (load (s32))
    RET undef $lr, implicit undef $w0
...