1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
define i1 @t32_3_1(i32 %X) nounwind {
; CHECK-LABEL: t32_3_1:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43691
; CHECK-NEXT: mov w9, #1431655765
; CHECK-NEXT: movk w8, #43690, lsl #16
; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%urem = urem i32 %X, 3
%cmp = icmp eq i32 %urem, 1
ret i1 %cmp
}
define i1 @t32_3_2(i32 %X) nounwind {
; CHECK-LABEL: t32_3_2:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43691
; CHECK-NEXT: mov w9, #-1431655766
; CHECK-NEXT: movk w8, #43690, lsl #16
; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: mov w9, #1431655765
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%urem = urem i32 %X, 3
%cmp = icmp eq i32 %urem, 2
ret i1 %cmp
}
define i1 @t32_5_1(i32 %X) nounwind {
; CHECK-LABEL: t32_5_1:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #52429
; CHECK-NEXT: mov w9, #858993459
; CHECK-NEXT: movk w8, #52428, lsl #16
; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%urem = urem i32 %X, 5
%cmp = icmp eq i32 %urem, 1
ret i1 %cmp
}
define i1 @t32_5_2(i32 %X) nounwind {
; CHECK-LABEL: t32_5_2:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #52429
; CHECK-NEXT: mov w9, #1717986918
; CHECK-NEXT: movk w8, #52428, lsl #16
; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: mov w9, #858993459
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%urem = urem i32 %X, 5
%cmp = icmp eq i32 %urem, 2
ret i1 %cmp
}
define i1 @t32_5_3(i32 %X) nounwind {
; CHECK-LABEL: t32_5_3:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #52429
; CHECK-NEXT: mov w9, #-1717986919
; CHECK-NEXT: movk w8, #52428, lsl #16
; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: mov w9, #858993459
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%urem = urem i32 %X, 5
%cmp = icmp eq i32 %urem, 3
ret i1 %cmp
}
define i1 @t32_5_4(i32 %X) nounwind {
; CHECK-LABEL: t32_5_4:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #52429
; CHECK-NEXT: mov w9, #-858993460
; CHECK-NEXT: movk w8, #52428, lsl #16
; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: mov w9, #858993459
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%urem = urem i32 %X, 5
%cmp = icmp eq i32 %urem, 4
ret i1 %cmp
}
define i1 @t32_6_1(i32 %X) nounwind {
; CHECK-LABEL: t32_6_1:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43691
; CHECK-NEXT: mov w9, #1431655765
; CHECK-NEXT: movk w8, #43690, lsl #16
; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: mov w9, #43691
; CHECK-NEXT: movk w9, #10922, lsl #16
; CHECK-NEXT: ror w8, w8, #1
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%urem = urem i32 %X, 6
%cmp = icmp eq i32 %urem, 1
ret i1 %cmp
}
define i1 @t32_6_2(i32 %X) nounwind {
; CHECK-LABEL: t32_6_2:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43691
; CHECK-NEXT: mov w9, #-1431655766
; CHECK-NEXT: movk w8, #43690, lsl #16
; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: mov w9, #43691
; CHECK-NEXT: movk w9, #10922, lsl #16
; CHECK-NEXT: ror w8, w8, #1
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%urem = urem i32 %X, 6
%cmp = icmp eq i32 %urem, 2
ret i1 %cmp
}
define i1 @t32_6_3(i32 %X) nounwind {
; CHECK-LABEL: t32_6_3:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43691
; CHECK-NEXT: mov w9, #43691
; CHECK-NEXT: movk w8, #43690, lsl #16
; CHECK-NEXT: movk w9, #10922, lsl #16
; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: sub w8, w8, #1
; CHECK-NEXT: ror w8, w8, #1
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%urem = urem i32 %X, 6
%cmp = icmp eq i32 %urem, 3
ret i1 %cmp
}
define i1 @t32_6_4(i32 %X) nounwind {
; CHECK-LABEL: t32_6_4:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43691
; CHECK-NEXT: sub w9, w0, #4
; CHECK-NEXT: movk w8, #43690, lsl #16
; CHECK-NEXT: mul w8, w9, w8
; CHECK-NEXT: mov w9, #43690
; CHECK-NEXT: movk w9, #10922, lsl #16
; CHECK-NEXT: ror w8, w8, #1
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%urem = urem i32 %X, 6
%cmp = icmp eq i32 %urem, 4
ret i1 %cmp
}
define i1 @t32_6_5(i32 %X) nounwind {
; CHECK-LABEL: t32_6_5:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43691
; CHECK-NEXT: sub w9, w0, #5
; CHECK-NEXT: movk w8, #43690, lsl #16
; CHECK-NEXT: mul w8, w9, w8
; CHECK-NEXT: mov w9, #43690
; CHECK-NEXT: movk w9, #10922, lsl #16
; CHECK-NEXT: ror w8, w8, #1
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%urem = urem i32 %X, 6
%cmp = icmp eq i32 %urem, 5
ret i1 %cmp
}
;-------------------------------------------------------------------------------
; Other widths.
define i1 @t16_3_2(i16 %X) nounwind {
; CHECK-LABEL: t16_3_2:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-21845
; CHECK-NEXT: mov w9, #-21846
; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: mov w9, #21845
; CHECK-NEXT: cmp w9, w8, uxth
; CHECK-NEXT: cset w0, hi
; CHECK-NEXT: ret
%urem = urem i16 %X, 3
%cmp = icmp eq i16 %urem, 2
ret i1 %cmp
}
define i1 @t8_3_2(i8 %X) nounwind {
; CHECK-LABEL: t8_3_2:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-85
; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: sub w8, w8, #86
; CHECK-NEXT: and w8, w8, #0xff
; CHECK-NEXT: cmp w8, #85
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%urem = urem i8 %X, 3
%cmp = icmp eq i8 %urem, 2
ret i1 %cmp
}
define i1 @t64_3_2(i64 %X) nounwind {
; CHECK-LABEL: t64_3_2:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-6148914691236517206
; CHECK-NEXT: mov x9, #-6148914691236517206
; CHECK-NEXT: movk x8, #43691
; CHECK-NEXT: madd x8, x0, x8, x9
; CHECK-NEXT: mov x9, #6148914691236517205
; CHECK-NEXT: cmp x8, x9
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%urem = urem i64 %X, 3
%cmp = icmp eq i64 %urem, 2
ret i1 %cmp
}
|
