File: clamp-fmed3-const-combine.ll

package info (click to toggle)
llvm-toolchain-14 1%3A14.0.6-12
  • links: PTS, VCS
  • area: main
  • in suites: bookworm
  • size: 1,496,180 kB
  • sloc: cpp: 5,593,972; ansic: 986,872; asm: 585,869; python: 184,223; objc: 72,530; lisp: 31,119; f90: 27,793; javascript: 9,780; pascal: 9,762; sh: 9,482; perl: 7,468; ml: 5,432; awk: 3,523; makefile: 2,538; xml: 953; cs: 573; fortran: 567
file content (124 lines) | stat: -rw-r--r-- 5,278 bytes parent folder | download | duplicates (4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s

define float @test_fmed3_f32_known_nnan_ieee_true(float %a) #0 {
; GFX10-LABEL: test_fmed3_f32_known_nnan_ieee_true:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    v_mul_f32_e64 v0, v0, 2.0 clamp
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %fmul = fmul float %a, 2.0
  %fmed = call nnan float @llvm.amdgcn.fmed3.f32(float %fmul, float 0.0, float 1.0)
  ret float %fmed
}

define half @test_fmed3_f16_known_nnan_ieee_false(half %a) #1 {
; GFX10-LABEL: test_fmed3_f16_known_nnan_ieee_false:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    v_mul_f16_e64 v0, v0, 2.0 clamp
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %fmul = fmul half %a, 2.0
  %fmed = call nnan half @llvm.amdgcn.fmed3.f16(half %fmul, half 0.0, half 1.0)
  ret half %fmed
}

; %fmin is known non-SNaN because fmin inputs are fcanonicalized
define float @test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true(float %a) #2 {
; GFX10-LABEL: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    v_max_f32_e32 v0, v0, v0
; GFX10-NEXT:    v_min_f32_e64 v0, 0x41200000, v0 clamp
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %fmin = call float @llvm.minnum.f32(float %a, float 10.0)
  %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmin, float 0.0, float 1.0)
  ret float %fmed
}

; input may be SNaN. It's safe to clamp since third operand in fmed3 is 0.0
define float @test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp_true(float %a) #2 {
; GFX10-LABEL: test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp_true:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    v_mul_f32_e64 v0, v0, 2.0 clamp
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %fmul = fmul float %a, 2.0
  %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmul, float 1.0, float 0.0)
  ret float %fmed
}

; global nnan function attribute always forces clamp combine

define float @test_fmed3_global_nnan(float %a) #3 {
; GFX10-LABEL: test_fmed3_global_nnan:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    v_mul_f32_e64 v0, v0, 2.0 clamp
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %fmul = fmul float %a, 2.0
  %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmul, float 0.0, float 1.0)
  ret float %fmed
}

; ------------------------------------------------------------------------------
; Negative patterns
; ------------------------------------------------------------------------------

; ieee=false requires known never NaN input
define float @test_fmed3_f32_maybe_NaN_ieee_false(float %a) #1 {
; GFX10-LABEL: test_fmed3_f32_maybe_NaN_ieee_false:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    v_mul_f32_e32 v0, 2.0, v0
; GFX10-NEXT:    v_med3_f32 v0, v0, 1.0, 0
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %fmul = fmul float %a, 2.0
  %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmul, float 1.0, float 0.0)
  ret float %fmed
}

; ieee=true input is known non-SNaN but dx10_clamp=false
define float @test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false(float %a) #4 {
; GFX10-LABEL: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    v_max_f32_e32 v0, v0, v0
; GFX10-NEXT:    v_min_f32_e32 v0, 0x41200000, v0
; GFX10-NEXT:    v_med3_f32 v0, v0, 0, 1.0
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %fmin = call float @llvm.minnum.f32(float %a, float 10.0)
  %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmin, float 0.0, float 1.0)
  ret float %fmed
}

; ieee=true dx10_clamp=true but input may be SNaN, clamp requires third operand in fmed3 to be 0.0
define float @test_fmed3_maybe_SNaN_input_ieee_true_dx10clamp_true(float %a) #2 {
; GFX10-LABEL: test_fmed3_maybe_SNaN_input_ieee_true_dx10clamp_true:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    v_mul_f32_e32 v0, 2.0, v0
; GFX10-NEXT:    v_med3_f32 v0, v0, 0, 1.0
; GFX10-NEXT:    s_setpc_b64 s[30:31]
  %fmul = fmul float %a, 2.0
  %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmul, float 0.0, float 1.0)
  ret float %fmed
}

declare half @llvm.amdgcn.fmed3.f16(half, half, half)
declare float @llvm.amdgcn.fmed3.f32(float, float, float)
declare float @llvm.minnum.f32(float, float)

attributes #0 = {"amdgpu-ieee"="true"}
attributes #1 = {"amdgpu-ieee"="false"}
attributes #2 = {"amdgpu-ieee"="true" "amdgpu-dx10-clamp"="true"}
attributes #3 = {"no-nans-fp-math"="true"}
attributes #4 = {"amdgpu-ieee"="true" "amdgpu-dx10-clamp"="false"}