1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
|
; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7
; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports
; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always
; using two shifts.
; Note that lsl, asr and lsr in Thumb are all encoded as 16-bit instructions
; and therefore must set flags. {{s?}} below denotes this, instead of
; duplicating tests.
; zext
define i8 @zext_1_8(i1 %a) nounwind ssp {
; v7-LABEL: zext_1_8:
; v7: and r0, r0, #1
%r = zext i1 %a to i8
ret i8 %r
}
define i16 @zext_1_16(i1 %a) nounwind ssp {
; v7-LABEL: zext_1_16:
; v7: and r0, r0, #1
%r = zext i1 %a to i16
ret i16 %r
}
define i32 @zext_1_32(i1 %a) nounwind ssp {
; v7-LABEL: zext_1_32:
; v7: and r0, r0, #1
%r = zext i1 %a to i32
ret i32 %r
}
define i16 @zext_8_16(i8 %a) nounwind ssp {
; v7-LABEL: zext_8_16:
; v7: and r0, r0, #255
%r = zext i8 %a to i16
ret i16 %r
}
define i32 @zext_8_32(i8 %a) nounwind ssp {
; v7-LABEL: zext_8_32:
; v7: and r0, r0, #255
%r = zext i8 %a to i32
ret i32 %r
}
define i32 @zext_16_32(i16 %a) nounwind ssp {
; v7-LABEL: zext_16_32:
; v7: uxth r0, r0
%r = zext i16 %a to i32
ret i32 %r
}
; sext
define i8 @sext_1_8(i1 %a) nounwind ssp {
; v7-LABEL: sext_1_8:
; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i8
ret i8 %r
}
define i16 @sext_1_16(i1 %a) nounwind ssp {
; v7-LABEL: sext_1_16:
; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i16
ret i16 %r
}
define i32 @sext_1_32(i1 %a) nounwind ssp {
; v7-LABEL: sext_1_32:
; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i32
ret i32 %r
}
define i16 @sext_8_16(i8 %a) nounwind ssp {
; v7-LABEL: sext_8_16:
; v7: sxtb r0, r0
%r = sext i8 %a to i16
ret i16 %r
}
define i32 @sext_8_32(i8 %a) nounwind ssp {
; v7-LABEL: sext_8_32:
; v7: sxtb r0, r0
%r = sext i8 %a to i32
ret i32 %r
}
define i32 @sext_16_32(i16 %a) nounwind ssp {
; v7-LABEL: sext_16_32:
; v7: sxth r0, r0
%r = sext i16 %a to i32
ret i32 %r
}
|
