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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass mir-canonicalizer -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s | FileCheck %s
--- |
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
define amdgpu_kernel void @f(i32 addrspace(1)* nocapture %arg) {
unreachable
}
...
---
name: f
alignment: 1
registers:
- { id: 0, class: sgpr_64 }
- { id: 1, class: sreg_64_xexec }
- { id: 2, class: sreg_64_xexec }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: sreg_64_xexec }
- { id: 5, class: sreg_64_xexec }
- { id: 6, class: sreg_64_xexec }
liveins:
- { reg: '$sgpr4_sgpr5', virtual-reg: '%4' }
body: |
bb.0:
liveins: $sgpr4_sgpr5
; CHECK: COPY
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
%0 = COPY $sgpr4_sgpr5
%1 = S_LOAD_DWORDX2_IMM %0, 0, 0 :: (non-temporal dereferenceable invariant load (s64) from `i64 addrspace(4)* undef`)
%2 = S_LOAD_DWORDX2_IMM %0, 0, 0 :: ( dereferenceable invariant load (s64) from `i64 addrspace(4)* undef`)
%3 = S_LOAD_DWORDX2_IMM %0, 0, 0 :: ( invariant load (s64) from `i64 addrspace(4)* undef`)
%4 = S_LOAD_DWORDX2_IMM %0, 0, 0 :: ( load (s64) from `i64 addrspace(4)* undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 0, 0 :: ( load (s64) from `i64 addrspace(2)* undef`)
%6 = S_LOAD_DWORDX2_IMM %0, 0, 0 :: ( load (s64) from `i64 addrspace(1)* undef`)
...
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