1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
|
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
; Test add with non-legal types
define void @add_i8(i8 %a, i8 %b) nounwind {
entry:
; PPC64: add_i8
%a.addr = alloca i8, align 4
%0 = add i8 %a, %b
; PPC64: add
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @add_i8_imm(i8 %a) nounwind {
entry:
; PPC64: add_i8_imm
%a.addr = alloca i8, align 4
%0 = add i8 %a, 22;
; PPC64: addi
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @add_i16(i16 %a, i16 %b) nounwind {
entry:
; PPC64: add_i16
%a.addr = alloca i16, align 4
%0 = add i16 %a, %b
; PPC64: add
store i16 %0, i16* %a.addr, align 4
ret void
}
define void @add_i16_imm(i16 %a, i16 %b) nounwind {
entry:
; PPC64: add_i16_imm
%a.addr = alloca i16, align 4
%0 = add i16 %a, 243;
; PPC64: addi
store i16 %0, i16* %a.addr, align 4
ret void
}
; Test or with non-legal types
define void @or_i8(i8 %a, i8 %b) nounwind {
entry:
; PPC64: or_i8
%a.addr = alloca i8, align 4
%0 = or i8 %a, %b
; PPC64: or
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @or_i8_imm(i8 %a) nounwind {
entry:
; PPC64: or_i8_imm
%a.addr = alloca i8, align 4
%0 = or i8 %a, -13;
; PPC64: ori
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @or_i16(i16 %a, i16 %b) nounwind {
entry:
; PPC64: or_i16
%a.addr = alloca i16, align 4
%0 = or i16 %a, %b
; PPC64: or
store i16 %0, i16* %a.addr, align 4
ret void
}
define void @or_i16_imm(i16 %a) nounwind {
entry:
; PPC64: or_i16_imm
%a.addr = alloca i16, align 4
%0 = or i16 %a, 273;
; PPC64: ori
store i16 %0, i16* %a.addr, align 4
ret void
}
; Test sub with non-legal types
define void @sub_i8(i8 %a, i8 %b) nounwind {
entry:
; PPC64: sub_i8
%a.addr = alloca i8, align 4
%0 = sub i8 %a, %b
; PPC64: sub
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @sub_i8_imm(i8 %a) nounwind {
entry:
; PPC64: sub_i8_imm
%a.addr = alloca i8, align 4
%0 = sub i8 %a, 22;
; PPC64: addi
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @sub_i16(i16 %a, i16 %b) nounwind {
entry:
; PPC64: sub_i16
%a.addr = alloca i16, align 4
%0 = sub i16 %a, %b
; PPC64: sub
store i16 %0, i16* %a.addr, align 4
ret void
}
define void @sub_i16_imm(i16 %a) nounwind {
entry:
; PPC64: sub_i16_imm
%a.addr = alloca i16, align 4
%0 = sub i16 %a, 247;
; PPC64: addi
store i16 %0, i16* %a.addr, align 4
ret void
}
define void @sub_i16_badimm(i16 %a) nounwind {
entry:
; PPC64: sub_i16_imm
%a.addr = alloca i16, align 4
%0 = sub i16 %a, -32768;
; PPC64: sub
store i16 %0, i16* %a.addr, align 4
ret void
}
|
