1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
@val = external local_unnamed_addr global i32, align 4
declare i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double>)
define dso_local signext i32 @xvtsqrtdp_and_1_eq(<2 x double> %input) {
; CHECK-LABEL: xvtsqrtdp_and_1_eq:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvtsqrtdp cr0, v2
; CHECK-NEXT: bnu cr0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: li r4, 100
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: stw r4, 0(r3)
; CHECK-NEXT: .LBB0_2: # %if.end
; CHECK-NEXT: li r3, 1
; CHECK-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
%1 = and i32 %0, 1
%cmp.not = icmp eq i32 %1, 0
br i1 %cmp.not, label %if.end, label %if.then
if.then: ; preds = %entry
store i32 100, i32* @val, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret i32 1
}
define dso_local signext i32 @xvtsqrtdp_and_2_eq(<2 x double> %input) {
; CHECK-LABEL: xvtsqrtdp_and_2_eq:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvtsqrtdp cr0, v2
; CHECK-NEXT: bne cr0, .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: li r4, 100
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: stw r4, 0(r3)
; CHECK-NEXT: .LBB1_2: # %if.end
; CHECK-NEXT: li r3, 1
; CHECK-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
%1 = and i32 %0, 2
%cmp.not = icmp eq i32 %1, 0
br i1 %cmp.not, label %if.end, label %if.then
if.then: ; preds = %entry
store i32 100, i32* @val, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret i32 1
}
define dso_local signext i32 @xvtsqrtdp_and_4_eq(<2 x double> %input) {
; CHECK-LABEL: xvtsqrtdp_and_4_eq:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvtsqrtdp cr0, v2
; CHECK-NEXT: ble cr0, .LBB2_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: li r4, 100
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: stw r4, 0(r3)
; CHECK-NEXT: .LBB2_2: # %if.end
; CHECK-NEXT: li r3, 1
; CHECK-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
%1 = and i32 %0, 4
%cmp.not = icmp eq i32 %1, 0
br i1 %cmp.not, label %if.end, label %if.then
if.then: ; preds = %entry
store i32 100, i32* @val, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret i32 1
}
define dso_local signext i32 @xvtsqrtdp_and_8_eq(<2 x double> %input) {
; CHECK-LABEL: xvtsqrtdp_and_8_eq:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvtsqrtdp cr0, v2
; CHECK-NEXT: bge cr0, .LBB3_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: li r4, 100
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: stw r4, 0(r3)
; CHECK-NEXT: .LBB3_2: # %if.end
; CHECK-NEXT: li r3, 1
; CHECK-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
%1 = and i32 %0, 8
%cmp.not = icmp eq i32 %1, 0
br i1 %cmp.not, label %if.end, label %if.then
if.then: ; preds = %entry
store i32 100, i32* @val, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret i32 1
}
define dso_local signext i32 @xvtsqrtdp_and_1_ne(<2 x double> %input) {
; CHECK-LABEL: xvtsqrtdp_and_1_ne:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvtsqrtdp cr0, v2
; CHECK-NEXT: bun cr0, .LBB4_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: li r4, 100
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: stw r4, 0(r3)
; CHECK-NEXT: .LBB4_2: # %if.end
; CHECK-NEXT: li r3, 1
; CHECK-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
%1 = and i32 %0, 1
%cmp.not = icmp ne i32 %1, 0
br i1 %cmp.not, label %if.end, label %if.then
if.then: ; preds = %entry
store i32 100, i32* @val, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret i32 1
}
define dso_local signext i32 @xvtsqrtdp_and_2_ne(<2 x double> %input) {
; CHECK-LABEL: xvtsqrtdp_and_2_ne:
; CHECK: # %bb.0: # %if.end
; CHECK-NEXT: li r3, 1
; CHECK-NEXT: blr
if.end: ; preds = %if.then, %entry
ret i32 1
}
define dso_local signext i32 @xvtsqrtdp_and_4_ne(<2 x double> %input) {
; CHECK-LABEL: xvtsqrtdp_and_4_ne:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvtsqrtdp cr0, v2
; CHECK-NEXT: bgt cr0, .LBB6_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: li r4, 100
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: stw r4, 0(r3)
; CHECK-NEXT: .LBB6_2: # %if.end
; CHECK-NEXT: li r3, 1
; CHECK-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
%1 = and i32 %0, 4
%cmp.not = icmp ne i32 %1, 0
br i1 %cmp.not, label %if.end, label %if.then
if.then: ; preds = %entry
store i32 100, i32* @val, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret i32 1
}
define dso_local signext i32 @xvtsqrtdp_and_8_ne(<2 x double> %input) {
; CHECK-LABEL: xvtsqrtdp_and_8_ne:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvtsqrtdp cr0, v2
; CHECK-NEXT: blt cr0, .LBB7_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: li r4, 100
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: stw r4, 0(r3)
; CHECK-NEXT: .LBB7_2: # %if.end
; CHECK-NEXT: li r3, 1
; CHECK-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)
%1 = and i32 %0, 8
%cmp.not = icmp ne i32 %1, 0
br i1 %cmp.not, label %if.end, label %if.then
if.then: ; preds = %entry
store i32 100, i32* @val, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret i32 1
}
|
