1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: < %s | FileCheck %s --check-prefix=CHECK-P10LE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: < %s | FileCheck %s --check-prefix=CHECK-P10BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9
define <8 x i16> @test1(i16* %a) {
; CHECK-P10LE-LABEL: test1:
; CHECK-P10LE: # %bb.0: # %entry
; CHECK-P10LE-NEXT: lxvrhx v2, 0, r3
; CHECK-P10LE-NEXT: blr
;
; CHECK-P10BE-LABEL: test1:
; CHECK-P10BE: # %bb.0: # %entry
; CHECK-P10BE-NEXT: lxsihzx v2, 0, r3
; CHECK-P10BE-NEXT: vsplth v2, v2, 3
; CHECK-P10BE-NEXT: blr
;
; CHECK-P9-LABEL: test1:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxsihzx v2, 0, r3
; CHECK-P9-NEXT: vsplth v2, v2, 3
; CHECK-P9-NEXT: blr
entry:
%0 = load i16, i16* %a, align 2
%vecinit = insertelement <8 x i16> undef, i16 %0, i32 0
ret <8 x i16> %vecinit
}
define <16 x i8> @test2(i8* %a) {
; CHECK-P10LE-LABEL: test2:
; CHECK-P10LE: # %bb.0: # %entry
; CHECK-P10LE-NEXT: lxvrbx v2, 0, r3
; CHECK-P10LE-NEXT: blr
;
; CHECK-P10BE-LABEL: test2:
; CHECK-P10BE: # %bb.0: # %entry
; CHECK-P10BE-NEXT: lxsibzx v2, 0, r3
; CHECK-P10BE-NEXT: vspltb v2, v2, 7
; CHECK-P10BE-NEXT: blr
;
; CHECK-P9-LABEL: test2:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxsibzx v2, 0, r3
; CHECK-P9-NEXT: vspltb v2, v2, 7
; CHECK-P9-NEXT: blr
entry:
%0 = load i8, i8* %a, align 1
%vecins = insertelement <16 x i8> undef, i8 %0, i32 0
ret <16 x i8> %vecins
}
|
