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|
# REQUIRES: asserts
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 -x=mir < %s \
# RUN: -debug-only=machine-scheduler -start-before=postmisched 2>&1 \
# RUN: -mattr=+fuse-zeromove,+fuse-cmp,+fuse-wideimm,+fuse-back2back \
# RUN: | FileCheck %s
# CHECK: add_mulld:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / MULLD - ADD8
---
name: add_mulld
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3, $x4, $x5
renamable $x4 = MULLD $x3, $x4
renamable $x3 = ADD8 killed renamable $x4, $x5
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
# CHECK: add_and:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / ADD8 - AND8
---
name: add_and
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3, $x4, $x5
renamable $x4 = ADD8 $x3, $x4
renamable $x3 = AND8 killed renamable $x4, $x5
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
# CHECK: xor_subf:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / XOR8 - SUBF8
---
name: xor_subf
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3, $x4, $x5
renamable $x4 = XOR8 $x3, $x4
renamable $x3 = SUBF8 killed renamable $x4, $x5
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
# CHECK: or_nand:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / OR8 - NAND8
---
name: or_nand
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3, $x4, $x5
renamable $x4 = OR8 $x3, $x4
renamable $x3 = NAND8 killed renamable $x4, $x5
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
# CHECK: vand_vand:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / VAND - VAND
---
name: vand_vand
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $v2, $v3, $v4
renamable $v2 = VAND $v3, $v2
renamable $v2 = VAND killed renamable $v2, $v4
BLR8 implicit $lr8, implicit $rm
...
# CHECK: vadd_vadd:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / VADDUDM - VADDUDM
---
name: vadd_vadd
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $v2, $v3, $v4
renamable $v2 = VADDUDM $v3, $v2
renamable $v2 = VADDUDM killed renamable $v2, $v4
BLR8 implicit $lr8, implicit $rm
...
# CHECK: sldi_add:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / RLDICR - ADD8
---
name: sldi_add
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3, $x4, $x5
renamable $x4 = RLDICR $x3, 3, 60
renamable $x3 = ADD8 killed renamable $x4, $x5
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
# CHECK: rldicl_xor:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / RLDICL - XOR8
---
name: rldicl_xor
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3, $x4, $x5
renamable $x4 = RLDICL $x3, 1, 0
renamable $x3 = XOR8 killed renamable $x4, $x5
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
# CHECK: rldicr_xor:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / RLDICR - XOR8
---
name: rldicr_xor
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3, $x4, $x5
renamable $x4 = RLDICR $x3, 1, 63
renamable $x3 = XOR8 killed renamable $x4, $x5
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
# CHECK: ori_oris:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / ORI8 - ORIS8
---
name: ori_oris
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3, $x4
renamable $x4 = ORI8 $x3, 63
renamable $x3 = ORIS8 killed renamable $x4, 20
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
# CHECK: load_cmp:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / LD - CMPDI
---
name: load_cmp
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x3, $x4, $x5
renamable $x3 = LD 0, killed renamable $x3
renamable $cr0 = CMPDI killed renamable $x3, 0
renamable $x3 = ISEL8 killed renamable $x5, killed renamable $x4, renamable $cr0lt, implicit killed $cr0
BLR8 implicit $lr8, implicit $rm, implicit $x3
# CHECK: back2back_1:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / VADDUBM - VSUBUBM
---
name: back2back_1
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $v2, $v3, $v4
renamable $v2 = VADDUBM $v3, $v2
renamable $v2 = VSUBUBM killed renamable $v2, $v4
BLR8 implicit $lr8, implicit $rm
# CHECK: back2back_2:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / XSABSDP - XSNEGDP
---
name: back2back_2
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $f1, $f2
renamable $f2 = XSABSDP $f1, implicit $rm
renamable $f1 = XSNEGDP killed renamable $f2, implicit $rm
BLR8 implicit $lr8, implicit $rm, implicit $f1
# CHECK: back2back_3:%bb.0
# CHECK: Macro fuse: SU(0) - SU(1) / VMAXFP - XVMINSP
---
name: back2back_3
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $v2, $v3, $v4
renamable $v3 = VMAXFP $v2, $v3
renamable $v2 = XVMINSP killed renamable $v3, $v4, implicit $rm
BLR8 implicit $lr8, implicit $rm, implicit $v2
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