1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,LE
define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
; BE-LABEL: test1:
; BE: # %bb.0:
; BE-NEXT: lxvw4x 0, 0, 3
; BE-NEXT: vspltisb 2, -1
; BE-NEXT: vslw 2, 2, 2
; BE-NEXT: xxland 0, 0, 34
; BE-NEXT: stxvw4x 0, 0, 3
; BE-NEXT: lxvw4x 0, 0, 4
; BE-NEXT: xxlandc 0, 0, 34
; BE-NEXT: stxvw4x 0, 0, 4
; BE-NEXT: lxvw4x 0, 0, 5
; BE-NEXT: xvabssp 0, 0
; BE-NEXT: stxvw4x 0, 0, 5
; BE-NEXT: blr
;
; LE-LABEL: test1:
; LE: # %bb.0:
; LE-NEXT: lvx 2, 0, 3
; LE-NEXT: vspltisb 3, -1
; LE-NEXT: vslw 3, 3, 3
; LE-NEXT: xxland 34, 34, 35
; LE-NEXT: stvx 2, 0, 3
; LE-NEXT: lvx 2, 0, 4
; LE-NEXT: xxlandc 34, 34, 35
; LE-NEXT: stvx 2, 0, 4
; LE-NEXT: lvx 2, 0, 5
; LE-NEXT: xvabssp 34, 34
; LE-NEXT: stvx 2, 0, 5
; LE-NEXT: blr
%tmp = load <4 x i32>, <4 x i32>* %P1 ; <<4 x i32>> [#uses=1]
%tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1]
store <4 x i32> %tmp4, <4 x i32>* %P1
%tmp7 = load <4 x i32>, <4 x i32>* %P2 ; <<4 x i32>> [#uses=1]
%tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1]
store <4 x i32> %tmp9, <4 x i32>* %P2
%tmp.upgrd.1 = load <4 x float>, <4 x float>* %P3 ; <<4 x float>> [#uses=1]
%tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32> ; <<4 x i32>> [#uses=1]
%tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1]
%tmp13 = bitcast <4 x i32> %tmp12 to <4 x float> ; <<4 x float>> [#uses=1]
store <4 x float> %tmp13, <4 x float>* %P3
ret void
}
define <4 x i32> @test_30() nounwind {
; CHECK-LABEL: test_30:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 2, 15
; CHECK-NEXT: vadduwm 2, 2, 2
; CHECK-NEXT: blr
ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
}
define <4 x i32> @test_29() nounwind {
; CHECK-LABEL: test_29:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 3, -16
; CHECK-NEXT: vspltisw 2, 13
; CHECK-NEXT: vsubuwm 2, 2, 3
; CHECK-NEXT: blr
ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
}
define <8 x i16> @test_n30() nounwind {
; CHECK-LABEL: test_n30:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltish 2, -15
; CHECK-NEXT: vadduhm 2, 2, 2
; CHECK-NEXT: blr
ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
}
define <16 x i8> @test_n104() nounwind {
; CHECK-LABEL: test_n104:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisb 2, -13
; CHECK-NEXT: vslb 2, 2, 2
; CHECK-NEXT: blr
ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
}
define <4 x i32> @test_vsldoi() nounwind {
; CHECK-LABEL: test_vsldoi:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 2, 2
; CHECK-NEXT: vsldoi 2, 2, 2, 1
; CHECK-NEXT: blr
ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
}
define <8 x i16> @test_vsldoi_65023() nounwind {
; CHECK-LABEL: test_vsldoi_65023:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltish 2, -3
; CHECK-NEXT: vsldoi 2, 2, 2, 1
; CHECK-NEXT: blr
ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >
}
define <4 x i32> @test_vsldoi_x16() nounwind {
; CHECK-LABEL: test_vsldoi_x16:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 2, -3
; CHECK-NEXT: vsldoi 2, 2, 2, 2
; CHECK-NEXT: blr
ret <4 x i32> <i32 -131073, i32 -131073, i32 -131073, i32 -131073>
}
define <4 x i32> @test_vsldoi_x24() nounwind {
; CHECK-LABEL: test_vsldoi_x24:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 2, -3
; CHECK-NEXT: vsldoi 2, 2, 2, 3
; CHECK-NEXT: blr
ret <4 x i32> <i32 -33554433, i32 -33554433, i32 -33554433, i32 -33554433>
}
define <4 x i32> @test_rol() nounwind {
; CHECK-LABEL: test_rol:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 2, -12
; CHECK-NEXT: vrlw 2, 2, 2
; CHECK-NEXT: blr
ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
}
|
