1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
; Basic shift support is tested as part of ALU.ll. This file ensures that
; shifts which may not be supported natively are lowered properly.
declare i64 @llvm.fshr.i64(i64, i64, i64)
declare i128 @llvm.fshr.i128(i128, i128, i128)
define i64 @lshr64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: lshr64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a3, a2, -32
; RV32I-NEXT: bltz a3, .LBB0_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srl a0, a1, a3
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: li a3, 31
; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: srl a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: lshr64:
; RV64I: # %bb.0:
; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i64 %a, %b
ret i64 %1
}
define i64 @lshr64_minsize(i64 %a, i64 %b) minsize nounwind {
; RV32I-LABEL: lshr64_minsize:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __lshrdi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: lshr64_minsize:
; RV64I: # %bb.0:
; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: ret
%1 = lshr i64 %a, %b
ret i64 %1
}
define i64 @ashr64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: ashr64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a3, a2, -32
; RV32I-NEXT: bltz a3, .LBB2_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sra a0, a1, a3
; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: li a3, 31
; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: sra a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: ashr64:
; RV64I: # %bb.0:
; RV64I-NEXT: sra a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i64 %a, %b
ret i64 %1
}
define i64 @ashr64_minsize(i64 %a, i64 %b) minsize nounwind {
; RV32I-LABEL: ashr64_minsize:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __ashrdi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: ashr64_minsize:
; RV64I: # %bb.0:
; RV64I-NEXT: sra a0, a0, a1
; RV64I-NEXT: ret
%1 = ashr i64 %a, %b
ret i64 %1
}
define i64 @shl64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: shl64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a3, a2, -32
; RV32I-NEXT: bltz a3, .LBB4_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sll a1, a0, a3
; RV32I-NEXT: li a0, 0
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: li a3, 31
; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: srl a3, a4, a3
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: sll a0, a0, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: shl64:
; RV64I: # %bb.0:
; RV64I-NEXT: sll a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i64 %a, %b
ret i64 %1
}
define i64 @shl64_minsize(i64 %a, i64 %b) minsize nounwind {
; RV32I-LABEL: shl64_minsize:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __ashldi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: shl64_minsize:
; RV64I: # %bb.0:
; RV64I-NEXT: sll a0, a0, a1
; RV64I-NEXT: ret
%1 = shl i64 %a, %b
ret i64 %1
}
define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: lshr128:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: li a3, 64
; RV32I-NEXT: sub t0, a3, a2
; RV32I-NEXT: li a6, 32
; RV32I-NEXT: sub t1, a6, a2
; RV32I-NEXT: li t2, 31
; RV32I-NEXT: bltz t1, .LBB6_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sll t6, a5, t1
; RV32I-NEXT: j .LBB6_3
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: sll a6, a4, t0
; RV32I-NEXT: sub a7, t2, t0
; RV32I-NEXT: srli t3, a5, 1
; RV32I-NEXT: srl a7, t3, a7
; RV32I-NEXT: or t6, a6, a7
; RV32I-NEXT: .LBB6_3:
; RV32I-NEXT: lw t5, 4(a1)
; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: bgez a6, .LBB6_5
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: srl a7, t5, a2
; RV32I-NEXT: or t6, t6, a7
; RV32I-NEXT: .LBB6_5:
; RV32I-NEXT: addi t4, a2, -96
; RV32I-NEXT: addi t3, a2, -64
; RV32I-NEXT: bltz t4, .LBB6_7
; RV32I-NEXT: # %bb.6:
; RV32I-NEXT: li a7, 0
; RV32I-NEXT: bgeu a2, a3, .LBB6_8
; RV32I-NEXT: j .LBB6_9
; RV32I-NEXT: .LBB6_7:
; RV32I-NEXT: srl a7, a4, t3
; RV32I-NEXT: bltu a2, a3, .LBB6_9
; RV32I-NEXT: .LBB6_8:
; RV32I-NEXT: mv t6, a7
; RV32I-NEXT: .LBB6_9:
; RV32I-NEXT: mv a7, t5
; RV32I-NEXT: beqz a2, .LBB6_11
; RV32I-NEXT: # %bb.10:
; RV32I-NEXT: mv a7, t6
; RV32I-NEXT: .LBB6_11:
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sub t2, t2, a2
; RV32I-NEXT: bltz a6, .LBB6_13
; RV32I-NEXT: # %bb.12:
; RV32I-NEXT: srl t5, t5, a6
; RV32I-NEXT: bltz t1, .LBB6_14
; RV32I-NEXT: j .LBB6_15
; RV32I-NEXT: .LBB6_13:
; RV32I-NEXT: srl t6, a1, a2
; RV32I-NEXT: slli t5, t5, 1
; RV32I-NEXT: sll t5, t5, t2
; RV32I-NEXT: or t5, t6, t5
; RV32I-NEXT: bgez t1, .LBB6_15
; RV32I-NEXT: .LBB6_14:
; RV32I-NEXT: sll t0, a5, t0
; RV32I-NEXT: or t5, t5, t0
; RV32I-NEXT: .LBB6_15:
; RV32I-NEXT: slli t0, a4, 1
; RV32I-NEXT: bltz t4, .LBB6_17
; RV32I-NEXT: # %bb.16:
; RV32I-NEXT: srl t1, a4, t4
; RV32I-NEXT: bgeu a2, a3, .LBB6_18
; RV32I-NEXT: j .LBB6_19
; RV32I-NEXT: .LBB6_17:
; RV32I-NEXT: li t1, 95
; RV32I-NEXT: sub t1, t1, a2
; RV32I-NEXT: sll t1, t0, t1
; RV32I-NEXT: srl t3, a5, t3
; RV32I-NEXT: or t1, t3, t1
; RV32I-NEXT: bltu a2, a3, .LBB6_19
; RV32I-NEXT: .LBB6_18:
; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: .LBB6_19:
; RV32I-NEXT: bnez a2, .LBB6_22
; RV32I-NEXT: # %bb.20:
; RV32I-NEXT: bltz a6, .LBB6_23
; RV32I-NEXT: .LBB6_21:
; RV32I-NEXT: srl a5, a4, a6
; RV32I-NEXT: bgeu a2, a3, .LBB6_24
; RV32I-NEXT: j .LBB6_25
; RV32I-NEXT: .LBB6_22:
; RV32I-NEXT: mv a1, t5
; RV32I-NEXT: bgez a6, .LBB6_21
; RV32I-NEXT: .LBB6_23:
; RV32I-NEXT: srl a5, a5, a2
; RV32I-NEXT: sll t0, t0, t2
; RV32I-NEXT: or a5, a5, t0
; RV32I-NEXT: bltu a2, a3, .LBB6_25
; RV32I-NEXT: .LBB6_24:
; RV32I-NEXT: li a5, 0
; RV32I-NEXT: .LBB6_25:
; RV32I-NEXT: bltz a6, .LBB6_27
; RV32I-NEXT: # %bb.26:
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: bgeu a2, a3, .LBB6_28
; RV32I-NEXT: j .LBB6_29
; RV32I-NEXT: .LBB6_27:
; RV32I-NEXT: srl a4, a4, a2
; RV32I-NEXT: bltu a2, a3, .LBB6_29
; RV32I-NEXT: .LBB6_28:
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: .LBB6_29:
; RV32I-NEXT: sw a4, 12(a0)
; RV32I-NEXT: sw a5, 8(a0)
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a7, 4(a0)
; RV32I-NEXT: ret
;
; RV64I-LABEL: lshr128:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB6_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: srl a0, a1, a3
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: li a3, 63
; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: slli a4, a1, 1
; RV64I-NEXT: sll a3, a4, a3
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: srl a1, a1, a2
; RV64I-NEXT: ret
%1 = lshr i128 %a, %b
ret i128 %1
}
define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: ashr128:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: li a3, 64
; RV32I-NEXT: sub t1, a3, a2
; RV32I-NEXT: li a6, 32
; RV32I-NEXT: sub t2, a6, a2
; RV32I-NEXT: li t4, 31
; RV32I-NEXT: bltz t2, .LBB7_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sll s0, a5, t2
; RV32I-NEXT: j .LBB7_3
; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: sll a6, a4, t1
; RV32I-NEXT: sub a7, t4, t1
; RV32I-NEXT: srli t0, a5, 1
; RV32I-NEXT: srl a7, t0, a7
; RV32I-NEXT: or s0, a6, a7
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: lw t6, 4(a1)
; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: bgez a6, .LBB7_5
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: srl a7, t6, a2
; RV32I-NEXT: or s0, s0, a7
; RV32I-NEXT: .LBB7_5:
; RV32I-NEXT: addi t3, a2, -64
; RV32I-NEXT: addi t5, a2, -96
; RV32I-NEXT: srai a7, a4, 31
; RV32I-NEXT: bltz t5, .LBB7_7
; RV32I-NEXT: # %bb.6:
; RV32I-NEXT: mv t0, a7
; RV32I-NEXT: bgeu a2, a3, .LBB7_8
; RV32I-NEXT: j .LBB7_9
; RV32I-NEXT: .LBB7_7:
; RV32I-NEXT: sra t0, a4, t3
; RV32I-NEXT: bltu a2, a3, .LBB7_9
; RV32I-NEXT: .LBB7_8:
; RV32I-NEXT: mv s0, t0
; RV32I-NEXT: .LBB7_9:
; RV32I-NEXT: mv t0, t6
; RV32I-NEXT: beqz a2, .LBB7_11
; RV32I-NEXT: # %bb.10:
; RV32I-NEXT: mv t0, s0
; RV32I-NEXT: .LBB7_11:
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sub t4, t4, a2
; RV32I-NEXT: bltz a6, .LBB7_13
; RV32I-NEXT: # %bb.12:
; RV32I-NEXT: srl t6, t6, a6
; RV32I-NEXT: bltz t2, .LBB7_14
; RV32I-NEXT: j .LBB7_15
; RV32I-NEXT: .LBB7_13:
; RV32I-NEXT: srl s0, a1, a2
; RV32I-NEXT: slli t6, t6, 1
; RV32I-NEXT: sll t6, t6, t4
; RV32I-NEXT: or t6, s0, t6
; RV32I-NEXT: bgez t2, .LBB7_15
; RV32I-NEXT: .LBB7_14:
; RV32I-NEXT: sll t1, a5, t1
; RV32I-NEXT: or t6, t6, t1
; RV32I-NEXT: .LBB7_15:
; RV32I-NEXT: slli t1, a4, 1
; RV32I-NEXT: bltz t5, .LBB7_17
; RV32I-NEXT: # %bb.16:
; RV32I-NEXT: sra t2, a4, t5
; RV32I-NEXT: bgeu a2, a3, .LBB7_18
; RV32I-NEXT: j .LBB7_19
; RV32I-NEXT: .LBB7_17:
; RV32I-NEXT: li t2, 95
; RV32I-NEXT: sub t2, t2, a2
; RV32I-NEXT: sll t2, t1, t2
; RV32I-NEXT: srl t3, a5, t3
; RV32I-NEXT: or t2, t3, t2
; RV32I-NEXT: bltu a2, a3, .LBB7_19
; RV32I-NEXT: .LBB7_18:
; RV32I-NEXT: mv t6, t2
; RV32I-NEXT: .LBB7_19:
; RV32I-NEXT: bnez a2, .LBB7_22
; RV32I-NEXT: # %bb.20:
; RV32I-NEXT: bltz a6, .LBB7_23
; RV32I-NEXT: .LBB7_21:
; RV32I-NEXT: sra a5, a4, a6
; RV32I-NEXT: bgeu a2, a3, .LBB7_24
; RV32I-NEXT: j .LBB7_25
; RV32I-NEXT: .LBB7_22:
; RV32I-NEXT: mv a1, t6
; RV32I-NEXT: bgez a6, .LBB7_21
; RV32I-NEXT: .LBB7_23:
; RV32I-NEXT: srl a5, a5, a2
; RV32I-NEXT: sll t1, t1, t4
; RV32I-NEXT: or a5, a5, t1
; RV32I-NEXT: bltu a2, a3, .LBB7_25
; RV32I-NEXT: .LBB7_24:
; RV32I-NEXT: mv a5, a7
; RV32I-NEXT: .LBB7_25:
; RV32I-NEXT: bltz a6, .LBB7_27
; RV32I-NEXT: # %bb.26:
; RV32I-NEXT: mv a4, a7
; RV32I-NEXT: bgeu a2, a3, .LBB7_28
; RV32I-NEXT: j .LBB7_29
; RV32I-NEXT: .LBB7_27:
; RV32I-NEXT: sra a4, a4, a2
; RV32I-NEXT: bltu a2, a3, .LBB7_29
; RV32I-NEXT: .LBB7_28:
; RV32I-NEXT: mv a4, a7
; RV32I-NEXT: .LBB7_29:
; RV32I-NEXT: sw a4, 12(a0)
; RV32I-NEXT: sw a5, 8(a0)
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw t0, 4(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: ashr128:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB7_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: sra a0, a1, a3
; RV64I-NEXT: srai a1, a1, 63
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB7_2:
; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: li a3, 63
; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: slli a4, a1, 1
; RV64I-NEXT: sll a3, a4, a3
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: sra a1, a1, a2
; RV64I-NEXT: ret
%1 = ashr i128 %a, %b
ret i128 %1
}
define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: shl128:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a5, 4(a1)
; RV32I-NEXT: lw a4, 0(a1)
; RV32I-NEXT: li a3, 64
; RV32I-NEXT: sub t0, a3, a2
; RV32I-NEXT: li a6, 32
; RV32I-NEXT: sub t1, a6, a2
; RV32I-NEXT: li t2, 31
; RV32I-NEXT: bltz t1, .LBB8_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srl t6, a5, t1
; RV32I-NEXT: j .LBB8_3
; RV32I-NEXT: .LBB8_2:
; RV32I-NEXT: srl a6, a4, t0
; RV32I-NEXT: sub a7, t2, t0
; RV32I-NEXT: slli t3, a5, 1
; RV32I-NEXT: sll a7, t3, a7
; RV32I-NEXT: or t6, a6, a7
; RV32I-NEXT: .LBB8_3:
; RV32I-NEXT: lw t5, 8(a1)
; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: bgez a6, .LBB8_5
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: sll a7, t5, a2
; RV32I-NEXT: or t6, t6, a7
; RV32I-NEXT: .LBB8_5:
; RV32I-NEXT: addi t4, a2, -96
; RV32I-NEXT: addi t3, a2, -64
; RV32I-NEXT: bltz t4, .LBB8_7
; RV32I-NEXT: # %bb.6:
; RV32I-NEXT: li a7, 0
; RV32I-NEXT: bgeu a2, a3, .LBB8_8
; RV32I-NEXT: j .LBB8_9
; RV32I-NEXT: .LBB8_7:
; RV32I-NEXT: sll a7, a4, t3
; RV32I-NEXT: bltu a2, a3, .LBB8_9
; RV32I-NEXT: .LBB8_8:
; RV32I-NEXT: mv t6, a7
; RV32I-NEXT: .LBB8_9:
; RV32I-NEXT: mv a7, t5
; RV32I-NEXT: beqz a2, .LBB8_11
; RV32I-NEXT: # %bb.10:
; RV32I-NEXT: mv a7, t6
; RV32I-NEXT: .LBB8_11:
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: sub t2, t2, a2
; RV32I-NEXT: bltz a6, .LBB8_13
; RV32I-NEXT: # %bb.12:
; RV32I-NEXT: sll t5, t5, a6
; RV32I-NEXT: bltz t1, .LBB8_14
; RV32I-NEXT: j .LBB8_15
; RV32I-NEXT: .LBB8_13:
; RV32I-NEXT: sll t6, a1, a2
; RV32I-NEXT: srli t5, t5, 1
; RV32I-NEXT: srl t5, t5, t2
; RV32I-NEXT: or t5, t6, t5
; RV32I-NEXT: bgez t1, .LBB8_15
; RV32I-NEXT: .LBB8_14:
; RV32I-NEXT: srl t0, a5, t0
; RV32I-NEXT: or t5, t5, t0
; RV32I-NEXT: .LBB8_15:
; RV32I-NEXT: srli t0, a4, 1
; RV32I-NEXT: bltz t4, .LBB8_17
; RV32I-NEXT: # %bb.16:
; RV32I-NEXT: sll t1, a4, t4
; RV32I-NEXT: bgeu a2, a3, .LBB8_18
; RV32I-NEXT: j .LBB8_19
; RV32I-NEXT: .LBB8_17:
; RV32I-NEXT: li t1, 95
; RV32I-NEXT: sub t1, t1, a2
; RV32I-NEXT: srl t1, t0, t1
; RV32I-NEXT: sll t3, a5, t3
; RV32I-NEXT: or t1, t3, t1
; RV32I-NEXT: bltu a2, a3, .LBB8_19
; RV32I-NEXT: .LBB8_18:
; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: .LBB8_19:
; RV32I-NEXT: bnez a2, .LBB8_22
; RV32I-NEXT: # %bb.20:
; RV32I-NEXT: bltz a6, .LBB8_23
; RV32I-NEXT: .LBB8_21:
; RV32I-NEXT: sll a5, a4, a6
; RV32I-NEXT: bgeu a2, a3, .LBB8_24
; RV32I-NEXT: j .LBB8_25
; RV32I-NEXT: .LBB8_22:
; RV32I-NEXT: mv a1, t5
; RV32I-NEXT: bgez a6, .LBB8_21
; RV32I-NEXT: .LBB8_23:
; RV32I-NEXT: sll a5, a5, a2
; RV32I-NEXT: srl t0, t0, t2
; RV32I-NEXT: or a5, a5, t0
; RV32I-NEXT: bltu a2, a3, .LBB8_25
; RV32I-NEXT: .LBB8_24:
; RV32I-NEXT: li a5, 0
; RV32I-NEXT: .LBB8_25:
; RV32I-NEXT: bltz a6, .LBB8_27
; RV32I-NEXT: # %bb.26:
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: bgeu a2, a3, .LBB8_28
; RV32I-NEXT: j .LBB8_29
; RV32I-NEXT: .LBB8_27:
; RV32I-NEXT: sll a4, a4, a2
; RV32I-NEXT: bltu a2, a3, .LBB8_29
; RV32I-NEXT: .LBB8_28:
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: .LBB8_29:
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: sw a7, 8(a0)
; RV32I-NEXT: ret
;
; RV64I-LABEL: shl128:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB8_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: sll a1, a0, a3
; RV64I-NEXT: li a0, 0
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB8_2:
; RV64I-NEXT: sll a1, a1, a2
; RV64I-NEXT: li a3, 63
; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: srli a4, a0, 1
; RV64I-NEXT: srl a3, a4, a3
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: sll a0, a0, a2
; RV64I-NEXT: ret
%1 = shl i128 %a, %b
ret i128 %1
}
define i64 @fshr64_minsize(i64 %a, i64 %b) minsize nounwind {
; RV32I-LABEL: fshr64_minsize:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a4, a2, 32
; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: beqz a4, .LBB9_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: .LBB9_2:
; RV32I-NEXT: srl a5, a3, a2
; RV32I-NEXT: beqz a4, .LBB9_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: .LBB9_4:
; RV32I-NEXT: slli a0, a1, 1
; RV32I-NEXT: not a4, a2
; RV32I-NEXT: sll a0, a0, a4
; RV32I-NEXT: or a0, a0, a5
; RV32I-NEXT: srl a1, a1, a2
; RV32I-NEXT: slli a2, a3, 1
; RV32I-NEXT: sll a2, a2, a4
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fshr64_minsize:
; RV64I: # %bb.0:
; RV64I-NEXT: srl a2, a0, a1
; RV64I-NEXT: neg a1, a1
; RV64I-NEXT: sll a0, a0, a1
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
%res = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)
ret i64 %res
}
define i128 @fshr128_minsize(i128 %a, i128 %b) minsize nounwind {
; RV32I-LABEL: fshr128_minsize:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw t2, 0(a1)
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a7, 4(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: andi t1, a2, 64
; RV32I-NEXT: mv t0, a7
; RV32I-NEXT: mv a4, t2
; RV32I-NEXT: beqz t1, .LBB10_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv t0, a1
; RV32I-NEXT: mv a4, a3
; RV32I-NEXT: .LBB10_2:
; RV32I-NEXT: andi a6, a2, 32
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: bnez a6, .LBB10_13
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: bnez t1, .LBB10_14
; RV32I-NEXT: .LBB10_4:
; RV32I-NEXT: beqz a6, .LBB10_6
; RV32I-NEXT: .LBB10_5:
; RV32I-NEXT: mv t0, a3
; RV32I-NEXT: .LBB10_6:
; RV32I-NEXT: slli t3, t0, 1
; RV32I-NEXT: not t2, a2
; RV32I-NEXT: beqz t1, .LBB10_8
; RV32I-NEXT: # %bb.7:
; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB10_8:
; RV32I-NEXT: srl a7, a5, a2
; RV32I-NEXT: sll t1, t3, t2
; RV32I-NEXT: srl t0, t0, a2
; RV32I-NEXT: beqz a6, .LBB10_10
; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: .LBB10_10:
; RV32I-NEXT: or a7, t1, a7
; RV32I-NEXT: slli t1, a3, 1
; RV32I-NEXT: sll t1, t1, t2
; RV32I-NEXT: or t0, t1, t0
; RV32I-NEXT: srl a3, a3, a2
; RV32I-NEXT: beqz a6, .LBB10_12
; RV32I-NEXT: # %bb.11:
; RV32I-NEXT: mv a1, a4
; RV32I-NEXT: .LBB10_12:
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a4, a4, t2
; RV32I-NEXT: or a3, a4, a3
; RV32I-NEXT: srl a1, a1, a2
; RV32I-NEXT: slli a2, a5, 1
; RV32I-NEXT: sll a2, a2, t2
; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: sw a3, 8(a0)
; RV32I-NEXT: sw t0, 4(a0)
; RV32I-NEXT: sw a7, 0(a0)
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB10_13:
; RV32I-NEXT: mv a5, t0
; RV32I-NEXT: beqz t1, .LBB10_4
; RV32I-NEXT: .LBB10_14:
; RV32I-NEXT: mv a3, t2
; RV32I-NEXT: bnez a6, .LBB10_5
; RV32I-NEXT: j .LBB10_6
;
; RV64I-LABEL: fshr128_minsize:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a4, a2, 64
; RV64I-NEXT: mv a3, a0
; RV64I-NEXT: beqz a4, .LBB10_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a3, a1
; RV64I-NEXT: .LBB10_2:
; RV64I-NEXT: srl a5, a3, a2
; RV64I-NEXT: beqz a4, .LBB10_4
; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: .LBB10_4:
; RV64I-NEXT: slli a0, a1, 1
; RV64I-NEXT: not a4, a2
; RV64I-NEXT: sll a0, a0, a4
; RV64I-NEXT: or a0, a0, a5
; RV64I-NEXT: srl a1, a1, a2
; RV64I-NEXT: slli a2, a3, 1
; RV64I-NEXT: sll a2, a2, a4
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: ret
%res = tail call i128 @llvm.fshr.i128(i128 %a, i128 %a, i128 %b)
ret i128 %res
}
|
