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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-- -mattr=+x87 -mattr=-sse -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the x87 fpsw and fpcw regs
--- |
declare float @llvm.sqrt.f32(float)
define void @f1(float* %a, float* %b) {
%1 = load float, float* %a, align 4
%2 = load float, float* %b, align 4
%sub = fsub float %1, %2
store float %sub, float* %a, align 4
ret void
}
define void @f2(double* %a, double* %b) {
%1 = load double, double* %a, align 8
%2 = load double, double* %b, align 8
%add = fadd double %1, %2
store double %add, double* %a, align 8
ret void
}
define void @f3(x86_fp80* %a, x86_fp80* %b) {
%1 = load x86_fp80, x86_fp80* %a, align 16
%2 = load x86_fp80, x86_fp80* %b, align 16
%mul = fmul x86_fp80 %1, %2
store x86_fp80 %mul, x86_fp80* %a, align 16
ret void
}
define void @f4(float* %a, float* %b) {
%1 = load float, float* %a, align 4
%2 = load float, float* %b, align 4
%div = fdiv float %1, %2
store float %div, float* %a, align 4
ret void
}
define void @f5(float* %val, double* %ret) {
%1 = load float, float* %val, align 4
%res = fpext float %1 to double
store double %res, double* %ret, align 8
ret void
}
define void @f6(double* %val, float* %ret) {
%1 = load double, double* %val, align 8
%res = fptrunc double %1 to float
store float %res, float* %ret, align 4
ret void
}
define void @f7(float* %a) {
%1 = load float, float* %a, align 4
%res = call float @llvm.sqrt.f32(float %1)
store float %res, float* %a, align 4
ret void
}
...
---
name: f1
alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.0 (%ir-block.0):
liveins: $rdi, $rsi
; CHECK-LABEL: name: f1
; CHECK: liveins: $rdi, $rsi
; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.a)
; CHECK: renamable $fp0 = SUB_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.b)
; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s32) into %ir.a)
; CHECK: RET 0
renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.a)
renamable $fp0 = SUB_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.b)
ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s32) into %ir.a)
RET 0
...
---
name: f2
alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.0 (%ir-block.0):
liveins: $rdi, $rsi
; CHECK-LABEL: name: f2
; CHECK: liveins: $rdi, $rsi
; CHECK: renamable $fp0 = LD_Fp64m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s64) from %ir.a)
; CHECK: renamable $fp0 = ADD_Fp64m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s64) from %ir.b)
; CHECK: ST_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s64) into %ir.a)
; CHECK: RET 0
renamable $fp0 = LD_Fp64m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s64) from %ir.a)
renamable $fp0 = ADD_Fp64m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s64) from %ir.b)
ST_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s64) into %ir.a)
RET 0
...
---
name: f3
alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.0 (%ir-block.0):
liveins: $rdi, $rsi
; CHECK-LABEL: name: f3
; CHECK: liveins: $rdi, $rsi
; CHECK: renamable $fp0 = LD_Fp80m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s80) from %ir.a, align 16)
; CHECK: renamable $fp1 = LD_Fp80m killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s80) from %ir.b, align 16)
; CHECK: renamable $fp0 = MUL_Fp80 killed renamable $fp0, killed renamable $fp1, implicit-def dead $fpsw, implicit $fpcw
; CHECK: ST_FpP80m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s80) into %ir.a, align 16)
; CHECK: RET 0
renamable $fp0 = LD_Fp80m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s80) from %ir.a, align 16)
renamable $fp1 = LD_Fp80m killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s80) from %ir.b, align 16)
renamable $fp0 = MUL_Fp80 killed renamable $fp0, killed renamable $fp1, implicit-def dead $fpsw, implicit $fpcw
ST_FpP80m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s80) into %ir.a, align 16)
RET 0
...
---
name: f4
alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.0 (%ir-block.0):
liveins: $rdi, $rsi
; CHECK-LABEL: name: f4
; CHECK: liveins: $rdi, $rsi
; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.a)
; CHECK: renamable $fp0 = DIV_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.b)
; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s32) into %ir.a)
; CHECK: RET 0
renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.a)
renamable $fp0 = DIV_Fp32m killed renamable $fp0, killed renamable $rsi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.b)
ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s32) into %ir.a)
RET 0
...
---
name: f5
alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.0 (%ir-block.0):
liveins: $rdi, $rsi
; CHECK-LABEL: name: f5
; CHECK: liveins: $rdi, $rsi
; CHECK: renamable $fp0 = LD_Fp32m64 killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.val)
; CHECK: ST_Fp64m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s64) into %ir.ret)
; CHECK: RET 0
renamable $fp0 = LD_Fp32m64 killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.val)
ST_Fp64m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s64) into %ir.ret)
RET 0
...
---
name: f6
alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
frameInfo:
maxAlignment: 4
stack:
- { id: 0, size: 4, alignment: 4 }
machineFunctionInfo: {}
body: |
bb.0 (%ir-block.0):
liveins: $rdi, $rsi
; CHECK-LABEL: name: f6
; CHECK: liveins: $rdi, $rsi
; CHECK: renamable $fp0 = LD_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s64) from %ir.val)
; CHECK: ST_Fp64m32 %stack.0, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s32) into %stack.0)
; CHECK: renamable $fp0 = LD_Fp32m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %stack.0)
; CHECK: ST_Fp32m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s32) into %ir.ret)
; CHECK: RET 0
renamable $fp0 = LD_Fp64m killed renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s64) from %ir.val)
ST_Fp64m32 %stack.0, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s32) into %stack.0)
renamable $fp0 = LD_Fp32m %stack.0, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %stack.0)
ST_Fp32m killed renamable $rsi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s32) into %ir.ret)
RET 0
...
---
name: f7
alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.0 (%ir-block.0):
liveins: $rdi
; CHECK-LABEL: name: f7
; CHECK: liveins: $rdi
; CHECK: renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.a)
; CHECK: renamable $fp0 = SQRT_Fp32 killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw
; CHECK: ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s32) into %ir.a)
; CHECK: RET 0
renamable $fp0 = LD_Fp32m renamable $rdi, 1, $noreg, 0, $noreg, implicit-def dead $fpsw, implicit $fpcw :: (load (s32) from %ir.a)
renamable $fp0 = SQRT_Fp32 killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw
ST_Fp32m killed renamable $rdi, 1, $noreg, 0, $noreg, killed renamable $fp0, implicit-def dead $fpsw, implicit $fpcw :: (store (s32) into %ir.a)
RET 0
...
|
