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@ RUN: llvm-mc -disassemble -triple armv7 -mcpu=cyclone %s | FileCheck %s
[0x00,0x22,0x00,0xe1]
[0x00,0x32,0x01,0xe1]
[0x00,0x52,0x02,0xe1]
[0x00,0x72,0x03,0xe1]
[0x00,0xb2,0x04,0xe1]
[0x00,0x12,0x05,0xe1]
[0x00,0x22,0x06,0xe1]
@ CHECK: mrs r2, r8_usr
@ CHECK: mrs r3, r9_usr
@ CHECK: mrs r5, r10_usr
@ CHECK: mrs r7, r11_usr
@ CHECK: mrs r11, r12_usr
@ CHECK: mrs r1, sp_usr
@ CHECK: mrs r2, lr_usr
[0x00,0x22,0x08,0xe1]
[0x00,0x32,0x09,0xe1]
[0x00,0x52,0x0a,0xe1]
[0x00,0x72,0x0b,0xe1]
[0x00,0xb2,0x0c,0xe1]
[0x00,0x12,0x0d,0xe1]
[0x00,0x22,0x0e,0xe1]
[0x00,0x32,0x4e,0xe1]
@ CHECK: mrs r2, r8_fiq
@ CHECK: mrs r3, r9_fiq
@ CHECK: mrs r5, r10_fiq
@ CHECK: mrs r7, r11_fiq
@ CHECK: mrs r11, r12_fiq
@ CHECK: mrs r1, sp_fiq
@ CHECK: mrs r2, lr_fiq
@ CHECK: mrs r3, SPSR_fiq
[0x00,0x43,0x00,0xe1]
[0x00,0x93,0x01,0xe1]
[0x00,0x13,0x40,0xe1]
@ CHECK: mrs r4, lr_irq
@ CHECK: mrs r9, sp_irq
@ CHECK: mrs r1, SPSR_irq
[0x00,0x13,0x02,0xe1]
[0x00,0x33,0x03,0xe1]
[0x00,0x53,0x42,0xe1]
@ CHECK: mrs r1, lr_svc
@ CHECK: mrs r3, sp_svc
@ CHECK: mrs r5, SPSR_svc
[0x00,0x53,0x04,0xe1]
[0x00,0x73,0x05,0xe1]
[0x00,0x93,0x44,0xe1]
@ CHECK: mrs r5, lr_abt
@ CHECK: mrs r7, sp_abt
@ CHECK: mrs r9, SPSR_abt
[0x00,0x93,0x06,0xe1]
[0x00,0xb3,0x07,0xe1]
[0x00,0xc3,0x46,0xe1]
@ CHECK: mrs r9, lr_und
@ CHECK: mrs r11, sp_und
@ CHECK: mrs r12, SPSR_und
[0x00,0x23,0x0c,0xe1]
[0x00,0x43,0x0d,0xe1]
[0x00,0x63,0x4c,0xe1]
@ CHECK: mrs r2, lr_mon
@ CHECK: mrs r4, sp_mon
@ CHECK: mrs r6, SPSR_mon
[0x00,0x63,0x0e,0xe1]
[0x00,0x83,0x0f,0xe1]
[0x00,0xa3,0x4e,0xe1]
@ CHECK: mrs r6, elr_hyp
@ CHECK: mrs r8, sp_hyp
@ CHECK: mrs r10, SPSR_hyp
[0x02,0xf2,0x20,0xe1]
[0x03,0xf2,0x21,0xe1]
[0x05,0xf2,0x22,0xe1]
[0x07,0xf2,0x23,0xe1]
[0x0b,0xf2,0x24,0xe1]
[0x01,0xf2,0x25,0xe1]
[0x02,0xf2,0x26,0xe1]
@ CHECK: msr r8_usr, r2
@ CHECK: msr r9_usr, r3
@ CHECK: msr r10_usr, r5
@ CHECK: msr r11_usr, r7
@ CHECK: msr r12_usr, r11
@ CHECK: msr sp_usr, r1
@ CHECK: msr lr_usr, r2
[0x02,0xf2,0x28,0xe1]
[0x03,0xf2,0x29,0xe1]
[0x05,0xf2,0x2a,0xe1]
[0x07,0xf2,0x2b,0xe1]
[0x0b,0xf2,0x2c,0xe1]
[0x01,0xf2,0x2d,0xe1]
[0x02,0xf2,0x2e,0xe1]
[0x03,0xf2,0x6e,0xe1]
@ CHECK: msr r8_fiq, r2
@ CHECK: msr r9_fiq, r3
@ CHECK: msr r10_fiq, r5
@ CHECK: msr r11_fiq, r7
@ CHECK: msr r12_fiq, r11
@ CHECK: msr sp_fiq, r1
@ CHECK: msr lr_fiq, r2
@ CHECK: msr SPSR_fiq, r3
[0x04,0xf3,0x20,0xe1]
[0x09,0xf3,0x21,0xe1]
[0x0b,0xf3,0x60,0xe1]
@ CHECK: msr lr_irq, r4
@ CHECK: msr sp_irq, r9
@ CHECK: msr SPSR_irq, r11
[0x01,0xf3,0x22,0xe1]
[0x03,0xf3,0x23,0xe1]
[0x05,0xf3,0x62,0xe1]
@ CHECK: msr lr_svc, r1
@ CHECK: msr sp_svc, r3
@ CHECK: msr SPSR_svc, r5
[0x05,0xf3,0x24,0xe1]
[0x07,0xf3,0x25,0xe1]
[0x09,0xf3,0x64,0xe1]
@ CHECK: msr lr_abt, r5
@ CHECK: msr sp_abt, r7
@ CHECK: msr SPSR_abt, r9
[0x09,0xf3,0x26,0xe1]
[0x0b,0xf3,0x27,0xe1]
[0x0c,0xf3,0x66,0xe1]
@ CHECK: msr lr_und, r9
@ CHECK: msr sp_und, r11
@ CHECK: msr SPSR_und, r12
[0x02,0xf3,0x2c,0xe1]
[0x04,0xf3,0x2d,0xe1]
[0x06,0xf3,0x6c,0xe1]
@ CHECK: msr lr_mon, r2
@ CHECK: msr sp_mon, r4
@ CHECK: msr SPSR_mon, r6
[0x06,0xf3,0x2e,0xe1]
[0x08,0xf3,0x2f,0xe1]
[0x0a,0xf3,0x6e,0xe1]
@ CHECK: msr elr_hyp, r6
@ CHECK: msr sp_hyp, r8
@ CHECK: msr SPSR_hyp, r10
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