1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
declare i8 @llvm.abs.i8(i8, i1)
declare i32 @llvm.abs.i32(i32, i1)
declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
declare <3 x i82> @llvm.abs.v3i82(<3 x i82>, i1)
declare void @llvm.assume(i1)
; abs preserves trailing zeros so the second and is unneeded
define i32 @abs_trailing_zeros(i32 %x) {
; CHECK-LABEL: @abs_trailing_zeros(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], -4
; CHECK-NEXT: [[ABS:%.*]] = call i32 @llvm.abs.i32(i32 [[AND]], i1 false)
; CHECK-NEXT: ret i32 [[ABS]]
;
%and = and i32 %x, -4
%abs = call i32 @llvm.abs.i32(i32 %and, i1 false)
%and2 = and i32 %abs, -2
ret i32 %and2
}
define <4 x i32> @abs_trailing_zeros_vec(<4 x i32> %x) {
; CHECK-LABEL: @abs_trailing_zeros_vec(
; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[X:%.*]], <i32 -4, i32 -8, i32 -16, i32 -32>
; CHECK-NEXT: [[ABS:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[AND]], i1 false)
; CHECK-NEXT: ret <4 x i32> [[ABS]]
;
%and = and <4 x i32> %x, <i32 -4, i32 -8, i32 -16, i32 -32>
%abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %and, i1 false)
%and2 = and <4 x i32> %abs, <i32 -2, i32 -2, i32 -2, i32 -2>
ret <4 x i32> %and2
}
; negative test, can't remove the second and based on trailing zeroes.
; FIXME: Could remove the first and using demanded bits.
define i32 @abs_trailing_zeros_negative(i32 %x) {
; CHECK-LABEL: @abs_trailing_zeros_negative(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], -2
; CHECK-NEXT: [[ABS:%.*]] = call i32 @llvm.abs.i32(i32 [[AND]], i1 false)
; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ABS]], -4
; CHECK-NEXT: ret i32 [[AND2]]
;
%and = and i32 %x, -2
%abs = call i32 @llvm.abs.i32(i32 %and, i1 false)
%and2 = and i32 %abs, -4
ret i32 %and2
}
define <4 x i32> @abs_trailing_zeros_negative_vec(<4 x i32> %x) {
; CHECK-LABEL: @abs_trailing_zeros_negative_vec(
; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[X:%.*]], <i32 -2, i32 -2, i32 -2, i32 -2>
; CHECK-NEXT: [[ABS:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[AND]], i1 false)
; CHECK-NEXT: [[AND2:%.*]] = and <4 x i32> [[ABS]], <i32 -4, i32 -4, i32 -4, i32 -4>
; CHECK-NEXT: ret <4 x i32> [[AND2]]
;
%and = and <4 x i32> %x, <i32 -2, i32 -2, i32 -2, i32 -2>
%abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %and, i1 false)
%and2 = and <4 x i32> %abs, <i32 -4, i32 -4, i32 -4, i32 -4>
ret <4 x i32> %and2
}
; Make sure we infer this add doesn't overflow. The input to the abs has 3
; sign bits, the abs reduces this to 2 sign bits.
define i32 @abs_signbits(i30 %x) {
; CHECK-LABEL: @abs_signbits(
; CHECK-NEXT: [[TMP1:%.*]] = call i30 @llvm.abs.i30(i30 [[X:%.*]], i1 false)
; CHECK-NEXT: [[NARROW:%.*]] = add nuw i30 [[TMP1]], 1
; CHECK-NEXT: [[ADD:%.*]] = zext i30 [[NARROW]] to i32
; CHECK-NEXT: ret i32 [[ADD]]
;
%ext = sext i30 %x to i32
%abs = call i32 @llvm.abs.i32(i32 %ext, i1 false)
%add = add i32 %abs, 1
ret i32 %add
}
define <4 x i32> @abs_signbits_vec(<4 x i30> %x) {
; CHECK-LABEL: @abs_signbits_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i30> @llvm.abs.v4i30(<4 x i30> [[X:%.*]], i1 false)
; CHECK-NEXT: [[NARROW:%.*]] = add nuw <4 x i30> [[TMP1]], <i30 1, i30 1, i30 1, i30 1>
; CHECK-NEXT: [[ADD:%.*]] = zext <4 x i30> [[NARROW]] to <4 x i32>
; CHECK-NEXT: ret <4 x i32> [[ADD]]
;
%ext = sext <4 x i30> %x to <4 x i32>
%abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %ext, i1 false)
%add = add <4 x i32> %abs, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %add
}
define i32 @abs_of_neg(i32 %x) {
; CHECK-LABEL: @abs_of_neg(
; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
; CHECK-NEXT: ret i32 [[B]]
;
%a = sub i32 0, %x
%b = call i32 @llvm.abs.i32(i32 %a, i1 false)
ret i32 %b
}
define <4 x i32> @abs_of_neg_vec(<4 x i32> %x) {
; CHECK-LABEL: @abs_of_neg_vec(
; CHECK-NEXT: [[B:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[X:%.*]], i1 false)
; CHECK-NEXT: ret <4 x i32> [[B]]
;
%a = sub nsw <4 x i32> zeroinitializer, %x
%b = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a, i1 false)
ret <4 x i32> %b
}
define i32 @abs_of_select_neg_true_val(i1 %b, i32 %x) {
; CHECK-LABEL: @abs_of_select_neg_true_val(
; CHECK-NEXT: [[ABS:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
; CHECK-NEXT: ret i32 [[ABS]]
;
%neg = sub i32 0, %x
%sel = select i1 %b, i32 %neg, i32 %x
%abs = call i32 @llvm.abs.i32(i32 %sel, i1 true)
ret i32 %abs
}
define <4 x i32> @abs_of_select_neg_false_val(<4 x i1> %b, <4 x i32> %x) {
; CHECK-LABEL: @abs_of_select_neg_false_val(
; CHECK-NEXT: [[ABS:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[X:%.*]], i1 false)
; CHECK-NEXT: ret <4 x i32> [[ABS]]
;
%neg = sub <4 x i32> zeroinitializer, %x
%sel = select <4 x i1> %b, <4 x i32> %x, <4 x i32> %neg
%abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sel, i1 false)
ret <4 x i32> %abs
}
define i32 @abs_dom_cond_nopoison(i32 %x) {
; CHECK-LABEL: @abs_dom_cond_nopoison(
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
; CHECK-NEXT: br i1 [[CMP]], label [[TRUE:%.*]], label [[FALSE:%.*]]
; CHECK: true:
; CHECK-NEXT: ret i32 [[X]]
; CHECK: false:
; CHECK-NEXT: [[A2:%.*]] = sub i32 0, [[X]]
; CHECK-NEXT: ret i32 [[A2]]
;
%cmp = icmp sge i32 %x, 0
br i1 %cmp, label %true, label %false
true:
%a1 = call i32 @llvm.abs.i32(i32 %x, i1 false)
ret i32 %a1
false:
%a2 = call i32 @llvm.abs.i32(i32 %x, i1 false)
ret i32 %a2
}
define i32 @abs_dom_cond_poison(i32 %x) {
; CHECK-LABEL: @abs_dom_cond_poison(
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
; CHECK-NEXT: br i1 [[CMP]], label [[TRUE:%.*]], label [[FALSE:%.*]]
; CHECK: true:
; CHECK-NEXT: ret i32 [[X]]
; CHECK: false:
; CHECK-NEXT: [[A2:%.*]] = sub nsw i32 0, [[X]]
; CHECK-NEXT: ret i32 [[A2]]
;
%cmp = icmp sge i32 %x, 0
br i1 %cmp, label %true, label %false
true:
%a1 = call i32 @llvm.abs.i32(i32 %x, i1 true)
ret i32 %a1
false:
%a2 = call i32 @llvm.abs.i32(i32 %x, i1 true)
ret i32 %a2
}
; Abs argument non-neg based on known bits.
define i32 @zext_abs(i31 %x) {
; CHECK-LABEL: @zext_abs(
; CHECK-NEXT: [[ZEXT:%.*]] = zext i31 [[X:%.*]] to i32
; CHECK-NEXT: ret i32 [[ZEXT]]
;
%zext = zext i31 %x to i32
%abs = call i32 @llvm.abs.i32(i32 %zext, i1 false)
ret i32 %abs
}
define <3 x i82> @lshr_abs(<3 x i82> %x) {
; CHECK-LABEL: @lshr_abs(
; CHECK-NEXT: [[LSHR:%.*]] = lshr <3 x i82> [[X:%.*]], <i82 1, i82 1, i82 1>
; CHECK-NEXT: ret <3 x i82> [[LSHR]]
;
%lshr = lshr <3 x i82> %x, <i82 1, i82 1, i82 1>
%abs = call <3 x i82> @llvm.abs.v3i82(<3 x i82> %lshr, i1 true)
ret <3 x i82> %abs
}
define i32 @and_abs(i32 %x) {
; CHECK-LABEL: @and_abs(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483644
; CHECK-NEXT: ret i32 [[AND]]
;
%and = and i32 %x, 2147483644
%abs = call i32 @llvm.abs.i32(i32 %and, i1 true)
ret i32 %abs
}
define <3 x i82> @select_abs(<3 x i1> %cond) {
; CHECK-LABEL: @select_abs(
; CHECK-NEXT: [[SEL:%.*]] = select <3 x i1> [[COND:%.*]], <3 x i82> zeroinitializer, <3 x i82> <i82 2147483647, i82 42, i82 1>
; CHECK-NEXT: ret <3 x i82> [[SEL]]
;
%sel = select <3 x i1> %cond, <3 x i82> zeroinitializer, <3 x i82> <i82 2147483647, i82 42, i82 1>
%abs = call <3 x i82> @llvm.abs.v3i82(<3 x i82> %sel, i1 false)
ret <3 x i82> %abs
}
define i32 @assume_abs(i32 %x) {
; CHECK-LABEL: @assume_abs(
; CHECK-NEXT: [[ASSUME:%.*]] = icmp sgt i32 [[X:%.*]], -1
; CHECK-NEXT: call void @llvm.assume(i1 [[ASSUME]])
; CHECK-NEXT: ret i32 [[X]]
;
%assume = icmp sge i32 %x, 0
call void @llvm.assume(i1 %assume)
%abs = call i32 @llvm.abs.i32(i32 %x, i1 true)
ret i32 %abs
}
; Abs argument negative based on known bits.
define i32 @abs_assume_neg(i32 %x) {
; CHECK-LABEL: @abs_assume_neg(
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: [[ABS:%.*]] = sub i32 0, [[X]]
; CHECK-NEXT: ret i32 [[ABS]]
;
%cmp = icmp slt i32 %x, 0
call void @llvm.assume(i1 %cmp)
%abs = call i32 @llvm.abs.i32(i32 %x, i1 false)
ret i32 %abs
}
define i32 @abs_known_neg(i16 %x) {
; CHECK-LABEL: @abs_known_neg(
; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[X:%.*]] to i32
; CHECK-NEXT: [[NEG_NEG:%.*]] = add nuw nsw i32 [[EXT]], 1
; CHECK-NEXT: ret i32 [[NEG_NEG]]
;
%ext = zext i16 %x to i32
%neg = sub nsw i32 -1, %ext
%abs = call i32 @llvm.abs.i32(i32 %neg, i1 false)
ret i32 %abs
}
define i1 @abs_eq_int_min_poison(i8 %x) {
; CHECK-LABEL: @abs_eq_int_min_poison(
; CHECK-NEXT: ret i1 false
;
%abs = call i8 @llvm.abs.i8(i8 %x, i1 true)
%cmp = icmp eq i8 %abs, -128
ret i1 %cmp
}
define i1 @abs_ne_int_min_poison(i8 %x) {
; CHECK-LABEL: @abs_ne_int_min_poison(
; CHECK-NEXT: ret i1 true
;
%abs = call i8 @llvm.abs.i8(i8 %x, i1 true)
%cmp = icmp ne i8 %abs, -128
ret i1 %cmp
}
define i1 @abs_eq_int_min_nopoison(i8 %x) {
; CHECK-LABEL: @abs_eq_int_min_nopoison(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[X:%.*]], -128
; CHECK-NEXT: ret i1 [[CMP]]
;
%abs = call i8 @llvm.abs.i8(i8 %x, i1 false)
%cmp = icmp eq i8 %abs, -128
ret i1 %cmp
}
define i1 @abs_ne_int_min_nopoison(i8 %x) {
; CHECK-LABEL: @abs_ne_int_min_nopoison(
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[X:%.*]], -128
; CHECK-NEXT: ret i1 [[CMP]]
;
%abs = call i8 @llvm.abs.i8(i8 %x, i1 false)
%cmp = icmp ne i8 %abs, -128
ret i1 %cmp
}
define i32 @abs_sext(i8 %x) {
; CHECK-LABEL: @abs_sext(
; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
; CHECK-NEXT: [[A:%.*]] = zext i8 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[A]]
;
%s = sext i8 %x to i32
%a = call i32 @llvm.abs.i32(i32 %s, i1 0)
ret i32 %a
}
define <3 x i82> @abs_nsw_sext(<3 x i7> %x) {
; CHECK-LABEL: @abs_nsw_sext(
; CHECK-NEXT: [[TMP1:%.*]] = call <3 x i7> @llvm.abs.v3i7(<3 x i7> [[X:%.*]], i1 false)
; CHECK-NEXT: [[A:%.*]] = zext <3 x i7> [[TMP1]] to <3 x i82>
; CHECK-NEXT: ret <3 x i82> [[A]]
;
%s = sext <3 x i7> %x to <3 x i82>
%a = call <3 x i82> @llvm.abs.v3i82(<3 x i82> %s, i1 1)
ret <3 x i82> %a
}
define i32 @abs_sext_extra_use(i8 %x, i32* %p) {
; CHECK-LABEL: @abs_sext_extra_use(
; CHECK-NEXT: [[S:%.*]] = sext i8 [[X:%.*]] to i32
; CHECK-NEXT: store i32 [[S]], i32* [[P:%.*]], align 4
; CHECK-NEXT: [[A:%.*]] = call i32 @llvm.abs.i32(i32 [[S]], i1 false)
; CHECK-NEXT: ret i32 [[A]]
;
%s = sext i8 %x to i32
store i32 %s, i32* %p
%a = call i32 @llvm.abs.i32(i32 %s, i1 0)
ret i32 %a
}
; PR48816
define i8 @trunc_abs_sext(i8 %x) {
; CHECK-LABEL: @trunc_abs_sext(
; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
; CHECK-NEXT: ret i8 [[TMP1]]
;
%s = sext i8 %x to i32
%a = tail call i32 @llvm.abs.i32(i32 %s, i1 true)
%t = trunc i32 %a to i8
ret i8 %t
}
define <4 x i8> @trunc_abs_sext_vec(<4 x i8> %x) {
; CHECK-LABEL: @trunc_abs_sext_vec(
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.abs.v4i8(<4 x i8> [[X:%.*]], i1 false)
; CHECK-NEXT: ret <4 x i8> [[TMP1]]
;
%s = sext <4 x i8> %x to <4 x i32>
%a = tail call <4 x i32> @llvm.abs.v4i32(<4 x i32> %s, i1 true)
%t = trunc <4 x i32> %a to <4 x i8>
ret <4 x i8> %t
}
; abs() doesn't change the low bit.
define i32 @demand_low_bit(i32 %x) {
; CHECK-LABEL: @demand_low_bit(
; CHECK-NEXT: [[R:%.*]] = and i32 [[X:%.*]], 1
; CHECK-NEXT: ret i32 [[R]]
;
%a = call i32 @llvm.abs.i32(i32 %x, i1 false)
%r = and i32 %a, 1
ret i32 %r
}
; Int min behavior doesn't affect the transform.
define <3 x i82> @demand_low_bit_int_min_is_poison(<3 x i82> %x) {
; CHECK-LABEL: @demand_low_bit_int_min_is_poison(
; CHECK-NEXT: [[R:%.*]] = shl <3 x i82> [[X:%.*]], <i82 81, i82 81, i82 81>
; CHECK-NEXT: ret <3 x i82> [[R]]
;
%a = call <3 x i82> @llvm.abs.v3i82(<3 x i82> %x, i1 true)
%r = shl <3 x i82> %a, <i82 81, i82 81, i82 81>
ret <3 x i82> %r
}
; Negative test - only low bit is allowed.
define i32 @demand_low_bits(i32 %x) {
; CHECK-LABEL: @demand_low_bits(
; CHECK-NEXT: [[A:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], 3
; CHECK-NEXT: ret i32 [[R]]
;
%a = call i32 @llvm.abs.i32(i32 %x, i1 false)
%r = and i32 %a, 3
ret i32 %r
}
define i32 @srem_by_2_int_min_is_poison(i32 %x) {
; CHECK-LABEL: @srem_by_2_int_min_is_poison(
; CHECK-NEXT: [[R:%.*]] = and i32 [[X:%.*]], 1
; CHECK-NEXT: ret i32 [[R]]
;
%s = srem i32 %x, 2
%r = call i32 @llvm.abs.i32(i32 %s, i1 true)
ret i32 %r
}
define <3 x i82> @srem_by_2(<3 x i82> %x, <3 x i82>* %p) {
; CHECK-LABEL: @srem_by_2(
; CHECK-NEXT: [[S:%.*]] = srem <3 x i82> [[X:%.*]], <i82 2, i82 2, i82 2>
; CHECK-NEXT: store <3 x i82> [[S]], <3 x i82>* [[P:%.*]], align 32
; CHECK-NEXT: [[R:%.*]] = and <3 x i82> [[X]], <i82 1, i82 1, i82 1>
; CHECK-NEXT: ret <3 x i82> [[R]]
;
%s = srem <3 x i82> %x, <i82 2, i82 2, i82 2>
store <3 x i82> %s, <3 x i82>* %p
%r = call <3 x i82> @llvm.abs.v3i82(<3 x i82> %s, i1 false)
ret <3 x i82> %r
}
; TODO: A more general transform could sink the srem and turn it into urem.
define i32 @srem_by_3(i32 %x) {
; CHECK-LABEL: @srem_by_3(
; CHECK-NEXT: [[S:%.*]] = srem i32 [[X:%.*]], 3
; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.abs.i32(i32 [[S]], i1 true)
; CHECK-NEXT: ret i32 [[R]]
;
%s = srem i32 %x, 3
%r = call i32 @llvm.abs.i32(i32 %s, i1 true)
ret i32 %r
}
|
