1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
target datalayout = "n8:16:32"
; Given pattern:
; (trunc (x << Q) to iDst) << K
; we should rewrite it as
; (trunc (x << (Q+K)) to iDst) iff (Q+K) u< iDst
; This is only valid for shl.
; THIS FOLD DOES *NOT* REQUIRE ANY 'nuw'/`nsw` FLAGS!
; Basic scalar test
define i16 @t0(i32 %x, i16 %y) {
; CHECK-LABEL: @t0(
; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i16
; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8
; CHECK-NEXT: ret i16 [[T5]]
;
%t0 = sub i16 32, %y
%t1 = zext i16 %t0 to i32
%t2 = shl i32 %x, %t1
%t3 = trunc i32 %t2 to i16
%t4 = add i16 %y, -24
%t5 = shl i16 %t3, %t4
ret i16 %t5
}
define <2 x i16> @t1_vec_splat(<2 x i32> %x, <2 x i16> %y) {
; CHECK-LABEL: @t1_vec_splat(
; CHECK-NEXT: [[X_TR:%.*]] = trunc <2 x i32> [[X:%.*]] to <2 x i16>
; CHECK-NEXT: [[T5:%.*]] = shl <2 x i16> [[X_TR]], <i16 8, i16 8>
; CHECK-NEXT: ret <2 x i16> [[T5]]
;
%t0 = sub <2 x i16> <i16 32, i16 32>, %y
%t1 = zext <2 x i16> %t0 to <2 x i32>
%t2 = shl <2 x i32> %x, %t1
%t3 = trunc <2 x i32> %t2 to <2 x i16>
%t4 = add <2 x i16> %y, <i16 -24, i16 -24>
%t5 = shl <2 x i16> %t3, %t4
ret <2 x i16> %t5
}
define <2 x i16> @t2_vec_nonsplat(<2 x i32> %x, <2 x i16> %y) {
; CHECK-LABEL: @t2_vec_nonsplat(
; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 8, i32 30>
; CHECK-NEXT: [[T5:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16>
; CHECK-NEXT: ret <2 x i16> [[T5]]
;
%t0 = sub <2 x i16> <i16 32, i16 30>, %y
%t1 = zext <2 x i16> %t0 to <2 x i32>
%t2 = shl <2 x i32> %x, %t1
%t3 = trunc <2 x i32> %t2 to <2 x i16>
%t4 = add <2 x i16> %y, <i16 -24, i16 0>
%t5 = shl <2 x i16> %t3, %t4
ret <2 x i16> %t5
}
; Basic vector tests
define <3 x i16> @t3_vec_nonsplat_undef0(<3 x i32> %x, <3 x i16> %y) {
; CHECK-LABEL: @t3_vec_nonsplat_undef0(
; CHECK-NEXT: [[X_TR:%.*]] = trunc <3 x i32> [[X:%.*]] to <3 x i16>
; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 0, i16 8>
; CHECK-NEXT: ret <3 x i16> [[T5]]
;
%t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
%t1 = zext <3 x i16> %t0 to <3 x i32>
%t2 = shl <3 x i32> %x, %t1
%t3 = trunc <3 x i32> %t2 to <3 x i16>
%t4 = add <3 x i16> %y, <i16 -24, i16 -24, i16 -24>
%t5 = shl <3 x i16> %t3, %t4
ret <3 x i16> %t5
}
define <3 x i16> @t4_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
; CHECK-LABEL: @t4_vec_nonsplat_undef1(
; CHECK-NEXT: [[X_TR:%.*]] = trunc <3 x i32> [[X:%.*]] to <3 x i16>
; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 0, i16 8>
; CHECK-NEXT: ret <3 x i16> [[T5]]
;
%t0 = sub <3 x i16> <i16 32, i16 32, i16 32>, %y
%t1 = zext <3 x i16> %t0 to <3 x i32>
%t2 = shl <3 x i32> %x, %t1
%t3 = trunc <3 x i32> %t2 to <3 x i16>
%t4 = add <3 x i16> %y, <i16 -24, i16 undef, i16 -24>
%t5 = shl <3 x i16> %t3, %t4
ret <3 x i16> %t5
}
define <3 x i16> @t5_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
; CHECK-LABEL: @t5_vec_nonsplat_undef1(
; CHECK-NEXT: [[X_TR:%.*]] = trunc <3 x i32> [[X:%.*]] to <3 x i16>
; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[X_TR]], <i16 8, i16 0, i16 8>
; CHECK-NEXT: ret <3 x i16> [[T5]]
;
%t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
%t1 = zext <3 x i16> %t0 to <3 x i32>
%t2 = shl <3 x i32> %x, %t1
%t3 = trunc <3 x i32> %t2 to <3 x i16>
%t4 = add <3 x i16> %y, <i16 -24, i16 undef, i16 -24>
%t5 = shl <3 x i16> %t3, %t4
ret <3 x i16> %t5
}
; One-use tests
declare void @use16(i16)
declare void @use32(i32)
define i16 @t6_extrause0(i32 %x, i16 %y) {
; CHECK-LABEL: @t6_extrause0(
; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
; CHECK-NEXT: call void @use16(i16 [[T3]])
; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X]] to i16
; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8
; CHECK-NEXT: ret i16 [[T5]]
;
%t0 = sub i16 32, %y
%t1 = zext i16 %t0 to i32
%t2 = shl i32 %x, %t1
%t3 = trunc i32 %t2 to i16
%t4 = add i16 %y, -24
call void @use16(i16 %t3)
%t5 = shl i16 %t3, %t4
ret i16 %t5
}
define i16 @t7_extrause1(i32 %x, i16 %y) {
; CHECK-LABEL: @t7_extrause1(
; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y:%.*]], -24
; CHECK-NEXT: call void @use16(i16 [[T4]])
; CHECK-NEXT: [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i16
; CHECK-NEXT: [[T5:%.*]] = shl i16 [[X_TR]], 8
; CHECK-NEXT: ret i16 [[T5]]
;
%t0 = sub i16 32, %y
%t1 = zext i16 %t0 to i32
%t2 = shl i32 %x, %t1
%t3 = trunc i32 %t2 to i16
%t4 = add i16 %y, -24
call void @use16(i16 %t4)
%t5 = shl i16 %t3, %t4
ret i16 %t5
}
define i16 @t8_extrause2(i32 %x, i16 %y) {
; CHECK-LABEL: @t8_extrause2(
; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -24
; CHECK-NEXT: call void @use16(i16 [[T3]])
; CHECK-NEXT: call void @use16(i16 [[T4]])
; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]
; CHECK-NEXT: ret i16 [[T5]]
;
%t0 = sub i16 32, %y
%t1 = zext i16 %t0 to i32
%t2 = shl i32 %x, %t1
%t3 = trunc i32 %t2 to i16
%t4 = add i16 %y, -24
call void @use16(i16 %t3)
call void @use16(i16 %t4)
%t5 = shl i16 %t3, %t4
ret i16 %t5
}
; No 'nuw'/'nsw' flags are to be propagated!
; But we can't test that, such IR does not reach that code.
; Negative tests
; Can't fold, total shift would be 32
define i16 @n11(i32 %x, i16 %y) {
; CHECK-LABEL: @n11(
; CHECK-NEXT: [[T0:%.*]] = sub i16 30, [[Y:%.*]]
; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -31
; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]
; CHECK-NEXT: ret i16 [[T5]]
;
%t0 = sub i16 30, %y
%t1 = zext i16 %t0 to i32
%t2 = shl i32 %x, %t1
%t3 = trunc i32 %t2 to i16
%t4 = add i16 %y, -31
%t5 = shl i16 %t3, %t4
ret i16 %t5
}
; Bit width mismatch of shift amount
@Y32 = global i32 42
@Y16 = global i16 42
define i16 @t01(i32 %x) {
; CHECK-LABEL: @t01(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], ptrtoint (i32* @Y32 to i32)
; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[T0]] to i16
; CHECK-NEXT: [[T2:%.*]] = shl i16 [[T1]], ptrtoint (i16* @Y16 to i16)
; CHECK-NEXT: ret i16 [[T2]]
;
%t0 = shl i32 %x, ptrtoint (i32* @Y32 to i32)
%t1 = trunc i32 %t0 to i16
%t2 = shl i16 %t1, ptrtoint (i16* @Y16 to i16)
ret i16 %t2
}
define i16 @shl_tr_shl_constant_shift_amount_uses(i32 %x) {
; CHECK-LABEL: @shl_tr_shl_constant_shift_amount_uses(
; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], 3
; CHECK-NEXT: call void @use32(i32 [[SHL]])
; CHECK-NEXT: [[TR:%.*]] = trunc i32 [[SHL]] to i16
; CHECK-NEXT: call void @use16(i16 [[TR]])
; CHECK-NEXT: [[R:%.*]] = shl i16 [[TR]], 4
; CHECK-NEXT: ret i16 [[R]]
;
%shl = shl i32 %x, 3
call void @use32(i32 %shl)
%tr = trunc i32 %shl to i16
call void @use16(i16 %tr)
%r = shl i16 %tr, 4
ret i16 %r
}
; This would infinite loop because we did not process the
; poison shift before trying to fold shift-of-shift. To reach
; the problematic transform, it needs a datalayout to specify
; that the narrow types are legal, but i64 is not.
define i1 @PR51657(i64 %x) {
; CHECK-LABEL: @PR51657(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 undef, label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
; CHECK: cond.false:
; CHECK-NEXT: br label [[COND_END]]
; CHECK: cond.end:
; CHECK-NEXT: ret i1 true
;
entry:
br i1 undef, label %cond.false, label %cond.end
cond.false:
%shl = shl i64 %x, 64
%conv26 = trunc i64 %shl to i32
%t1 = trunc i64 %shl to i8
br label %cond.end
cond.end:
%cond = phi i32 [ %conv26, %cond.false ], [ 0, %entry ]
%t2 = phi i8 [ %t1, %cond.false ], [ 0, %entry ]
%conv27 = sext i8 %t2 to i32
%eq = icmp eq i32 %cond, %conv27
ret i1 %eq
}
define i16 @extra_use_on_first_shift(i32 %x) {
; CHECK-LABEL: @extra_use_on_first_shift(
; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 3
; CHECK-NEXT: call void @use32(i32 [[A]])
; CHECK-NEXT: [[TR:%.*]] = trunc i32 [[A]] to i16
; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[TR]], 6
; CHECK-NEXT: ret i16 [[SH]]
;
%a = ashr i32 %x, 3
call void @use32(i32 %a)
%tr = trunc i32 %a to i16
%sh = lshr i16 %tr, 6
ret i16 %sh
}
|
