File: A55-2-skewed-alu.s

package info (click to toggle)
llvm-toolchain-14 1%3A14.0.6-12
  • links: PTS, VCS
  • area: main
  • in suites: bookworm
  • size: 1,496,180 kB
  • sloc: cpp: 5,593,972; ansic: 986,872; asm: 585,869; python: 184,223; objc: 72,530; lisp: 31,119; f90: 27,793; javascript: 9,780; pascal: 9,762; sh: 9,482; perl: 7,468; ml: 5,432; awk: 3,523; makefile: 2,538; xml: 953; cs: 573; fortran: 567
file content (18 lines) | stat: -rw-r--r-- 596 bytes parent folder | download | duplicates (21) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
 
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-views=false --summary-view --iterations=1000 < %s | FileCheck %s
# CHECK: IPC:
# CHECK-SAME: 2.00
#
# XFAIL: *
#
# Cortex-A55 has a secondary skewed ALU in the Ex1 stage for simple
# ALU instructions that do not require shifting or saturation
# resources. Results from the skewed ALU are available 1 cycle earlier.
#
# This features allows the first and the second instruction to be
# dual-issued despite a register dependency (w8).
#
# MCA and LLVM scheduling model do not support this yet.

add	w8, w8, #1
add	w10, w8, #1
add	w12, w8, #1