File: instr-reduce.mir

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# RUN: llvm-reduce -mtriple=riscv32 --test %python --test-arg %p/instr-reduce.py %s -o %t
# RUN: cat %t | FileCheck --match-full-lines %s

# REQUIRES: riscv-registered-target

# Verify that after reduction the following instruction sequence remains. The
# interestingness-test 'instr-reduce.py' matches a '%[0-9]+:gpr = ADDI %[0-9]+, 5'
# pattern in the output and that combined with that the MIR has to be valid
# (pass verify) results in the given sequence.

# CHECK:      %0:gpr = COPY $x10
# CHECK-NEXT: %2:gpr = ADDI %0, 5
# CHECK-NEXT: PseudoRET implicit $x10

...
---
name:            f
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10

    %10:gpr = COPY $x10
    %20:gpr = ADDI %10, 1
    %30:gpr = ADDI %20, 5
    %40:gpr = ADDI %30, 9
    $x10 = COPY %40
    PseudoRET implicit $x10
...
---