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llvm-toolchain-14 1%3A14.0.6-16
- links: PTS, VCS
- area: main
- in suites: sid
- size: 1,496,368 kB
- sloc: cpp: 5,593,980; ansic: 986,873; asm: 585,869; python: 184,223; objc: 72,530; lisp: 31,119; f90: 27,793; javascript: 9,780; pascal: 9,762; sh: 9,482; perl: 7,468; ml: 5,432; awk: 3,523; makefile: 2,547; xml: 953; cs: 573; fortran: 567
Folder: altera-kernel-name-restriction
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.. (parent) | |||
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d | rwxr-xr-x | 28 | otherdir |
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d | rwxr-xr-x | 83 | some |
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d | rwxr-xr-x | 31 | somedir |
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d | rwxr-xr-x | 69 | uppercase |
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- | rw-r--r-- | 26 | Verilog.cl |
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- | rw-r--r-- | 25 | kernel.cl |
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- | rw-r--r-- | 26 | kernel.h |
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- | rw-r--r-- | 31 | other_Verilog.cl |
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- | rw-r--r-- | 29 | otherthing.cl |
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- | rw-r--r-- | 29 | some_kernel.cl |
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- | rw-r--r-- | 24 | thing.h |
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- | rw-r--r-- | 27 | verilog.h |
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- | rw-r--r-- | 24 | vhdl.CL |
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- | rw-r--r-- | 24 | vhdl.h |
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- | rw-r--r-- | 32 | vhdl_number_two.cl |