1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
|
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbr -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV32ZBR
// RV32ZBR-LABEL: @crc32_b(
// RV32ZBR-NEXT: entry:
// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.b.i32(i32 [[TMP0]])
// RV32ZBR-NEXT: ret i32 [[TMP1]]
//
long crc32_b(long a) {
return __builtin_riscv_crc32_b(a);
}
// RV32ZBR-LABEL: @crc32_h(
// RV32ZBR-NEXT: entry:
// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.h.i32(i32 [[TMP0]])
// RV32ZBR-NEXT: ret i32 [[TMP1]]
//
long crc32_h(long a) {
return __builtin_riscv_crc32_h(a);
}
// RV32ZBR-LABEL: @crc32_w(
// RV32ZBR-NEXT: entry:
// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.w.i32(i32 [[TMP0]])
// RV32ZBR-NEXT: ret i32 [[TMP1]]
//
long crc32_w(long a) {
return __builtin_riscv_crc32_w(a);
}
// RV32ZBR-LABEL: @crc32c_b(
// RV32ZBR-NEXT: entry:
// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.b.i32(i32 [[TMP0]])
// RV32ZBR-NEXT: ret i32 [[TMP1]]
//
long crc32c_b(long a) {
return __builtin_riscv_crc32c_b(a);
}
// RV32ZBR-LABEL: @crc32c_h(
// RV32ZBR-NEXT: entry:
// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.h.i32(i32 [[TMP0]])
// RV32ZBR-NEXT: ret i32 [[TMP1]]
//
long crc32c_h(long a) {
return __builtin_riscv_crc32c_h(a);
}
// RV32ZBR-LABEL: @crc32c_w(
// RV32ZBR-NEXT: entry:
// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.w.i32(i32 [[TMP0]])
// RV32ZBR-NEXT: ret i32 [[TMP1]]
//
long crc32c_w(long a) {
return __builtin_riscv_crc32c_w(a);
}
|
