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<span id="amdgpu-synid-gfx10-vaddr-4"></span><h1>vaddr<a class="headerlink" href="#vaddr" title="Permalink to this headline">ΒΆ</a></h1>
<p>Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.</p>
<p>This operand may be specified using either <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">standard VGPR syntax</span></a> or special <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-nsa"><span class="std std-ref">NSA VGPR syntax</span></a>.</p>
<p><em>Size:</em> 1-13 dwords. Actual size depends on syntax, opcode, <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-dim"><span class="std std-ref">dim</span></a> and <a class="reference internal" href="../AMDGPUModifierSyntax.html#amdgpu-synid-a16"><span class="std std-ref">a16</span></a>.</p>
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<li><p>If specified using <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-nsa"><span class="std std-ref">NSA VGPR syntax</span></a>, the size is 1-13 dwords.</p></li>
<li><p>If specified using <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">standard VGPR syntax</span></a>, the size is 1-8 dwords. Opcodes which require more than 8 dwords for address size must specify 16 dwords due to a limited range of supported register sequences.</p></li>
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<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
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