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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -o - %s | FileCheck %s
// CHECK-LABEL: @add1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: store half [[A:%.*]], ptr [[A_ADDR]], align 2
// CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2
// CHECK-NEXT: [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
// CHECK-NEXT: ret half [[ADD]]
//
_Float16 add1(_Float16 a, _Float16 b) {
return a + b;
}
// CHECK-LABEL: @add2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: [[C_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: store half [[A:%.*]], ptr [[A_ADDR]], align 2
// CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 2
// CHECK-NEXT: store half [[C:%.*]], ptr [[C_ADDR]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2
// CHECK-NEXT: [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
// CHECK-NEXT: [[TMP2:%.*]] = load half, ptr [[C_ADDR]], align 2
// CHECK-NEXT: [[ADD1:%.*]] = fadd half [[ADD]], [[TMP2]]
// CHECK-NEXT: ret half [[ADD1]]
//
_Float16 add2(_Float16 a, _Float16 b, _Float16 c) {
return a + b + c;
}
// CHECK-LABEL: @div(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: store half [[A:%.*]], ptr [[A_ADDR]], align 2
// CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2
// CHECK-NEXT: [[DIV:%.*]] = fdiv half [[TMP0]], [[TMP1]]
// CHECK-NEXT: ret half [[DIV]]
//
_Float16 div(_Float16 a, _Float16 b) {
return a / b;
}
// CHECK-LABEL: @mul(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: store half [[A:%.*]], ptr [[A_ADDR]], align 2
// CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2
// CHECK-NEXT: [[MUL:%.*]] = fmul half [[TMP0]], [[TMP1]]
// CHECK-NEXT: ret half [[MUL]]
//
_Float16 mul(_Float16 a, _Float16 b) {
return a * b;
}
// CHECK-LABEL: @add_and_mul1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: [[C_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: [[D_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: store half [[A:%.*]], ptr [[A_ADDR]], align 2
// CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 2
// CHECK-NEXT: store half [[C:%.*]], ptr [[C_ADDR]], align 2
// CHECK-NEXT: store half [[D:%.*]], ptr [[D_ADDR]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2
// CHECK-NEXT: [[MUL:%.*]] = fmul half [[TMP0]], [[TMP1]]
// CHECK-NEXT: [[TMP2:%.*]] = load half, ptr [[C_ADDR]], align 2
// CHECK-NEXT: [[TMP3:%.*]] = load half, ptr [[D_ADDR]], align 2
// CHECK-NEXT: [[MUL1:%.*]] = fmul half [[TMP2]], [[TMP3]]
// CHECK-NEXT: [[ADD:%.*]] = fadd half [[MUL]], [[MUL1]]
// CHECK-NEXT: ret half [[ADD]]
//
_Float16 add_and_mul1(_Float16 a, _Float16 b, _Float16 c, _Float16 d) {
return a * b + c * d;
}
// CHECK-LABEL: @add_and_mul2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: [[C_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: [[D_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: store half [[A:%.*]], ptr [[A_ADDR]], align 2
// CHECK-NEXT: store half [[B:%.*]], ptr [[B_ADDR]], align 2
// CHECK-NEXT: store half [[C:%.*]], ptr [[C_ADDR]], align 2
// CHECK-NEXT: store half [[D:%.*]], ptr [[D_ADDR]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2
// CHECK-NEXT: [[MUL:%.*]] = fmul half 0xH4600, [[TMP1]]
// CHECK-NEXT: [[SUB:%.*]] = fsub half [[TMP0]], [[MUL]]
// CHECK-NEXT: [[TMP2:%.*]] = load half, ptr [[C_ADDR]], align 2
// CHECK-NEXT: [[ADD:%.*]] = fadd half [[SUB]], [[TMP2]]
// CHECK-NEXT: ret half [[ADD]]
//
_Float16 add_and_mul2(_Float16 a, _Float16 b, _Float16 c, _Float16 d) {
return (a - 6 * b) + c;
}
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