1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt -passes='print<cost-model>' 2>&1 -disable-output -mtriple aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
define void @test_urem_srem_expand() {
; CHECK-LABEL: 'test_urem_srem_expand'
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %legal_type_urem_0 = urem <vscale x 16 x i8> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %legal_type_urem_1 = urem <vscale x 8 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %legal_type_urem_2 = urem <vscale x 4 x i32> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %legal_type_urem_3 = urem <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %legal_type_srem_0 = srem <vscale x 16 x i8> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %legal_type_srem_1 = srem <vscale x 8 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %legal_type_srem_2 = srem <vscale x 4 x i32> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %legal_type_srem_3 = srem <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %split_type_urem_0 = urem <vscale x 32 x i8> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %split_type_urem_1 = urem <vscale x 16 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %split_type_urem_2 = urem <vscale x 8 x i32> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %split_type_urem_3 = urem <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %split_type_srem_0 = srem <vscale x 32 x i8> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %split_type_srem_1 = srem <vscale x 16 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %split_type_srem_2 = srem <vscale x 8 x i32> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %split_type_srem_3 = srem <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %widen_type_urem_0 = urem <vscale x 31 x i8> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %widen_type_urem_1 = urem <vscale x 15 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %widen_type_urem_2 = urem <vscale x 7 x i32> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %widen_type_urem_3 = urem <vscale x 3 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %widen_type_srem_0 = srem <vscale x 31 x i8> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %widen_type_srem_1 = srem <vscale x 15 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %widen_type_srem_2 = srem <vscale x 7 x i32> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %widen_type_srem_3 = srem <vscale x 3 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
entry:
%legal_type_urem_0 = urem <vscale x 16 x i8> undef, undef
%legal_type_urem_1 = urem <vscale x 8 x i16> undef, undef
%legal_type_urem_2 = urem <vscale x 4 x i32> undef, undef
%legal_type_urem_3 = urem <vscale x 2 x i64> undef, undef
%legal_type_srem_0 = srem <vscale x 16 x i8> undef, undef
%legal_type_srem_1 = srem <vscale x 8 x i16> undef, undef
%legal_type_srem_2 = srem <vscale x 4 x i32> undef, undef
%legal_type_srem_3 = srem <vscale x 2 x i64> undef, undef
%split_type_urem_0 = urem <vscale x 32 x i8> undef, undef
%split_type_urem_1 = urem <vscale x 16 x i16> undef, undef
%split_type_urem_2 = urem <vscale x 8 x i32> undef, undef
%split_type_urem_3 = urem <vscale x 4 x i64> undef, undef
%split_type_srem_0 = srem <vscale x 32 x i8> undef, undef
%split_type_srem_1 = srem <vscale x 16 x i16> undef, undef
%split_type_srem_2 = srem <vscale x 8 x i32> undef, undef
%split_type_srem_3 = srem <vscale x 4 x i64> undef, undef
%widen_type_urem_0 = urem <vscale x 31 x i8> undef, undef
%widen_type_urem_1 = urem <vscale x 15 x i16> undef, undef
%widen_type_urem_2 = urem <vscale x 7 x i32> undef, undef
%widen_type_urem_3 = urem <vscale x 3 x i64> undef, undef
%widen_type_srem_0 = srem <vscale x 31 x i8> undef, undef
%widen_type_srem_1 = srem <vscale x 15 x i16> undef, undef
%widen_type_srem_2 = srem <vscale x 7 x i32> undef, undef
%widen_type_srem_3 = srem <vscale x 3 x i64> undef, undef
ret void
}
|
