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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
---
name: abs_s32
liveins:
body: |
bb.0:
; CHECK-LABEL: name: abs_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s64)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ASHR]]
; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]
; CHECK: $w0 = COPY [[XOR]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = G_ABS %0(s32)
$w0 = COPY %1(s32)
...
---
name: abs_s64
liveins:
body: |
bb.0:
; CHECK-LABEL: name: abs_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64)
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ASHR]]
; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]]
; CHECK: $x0 = COPY [[XOR]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = G_ABS %0(s64)
$x0 = COPY %1(s64)
...
---
name: abs_v4s16
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: abs_v4s16
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[ABS:%[0-9]+]]:_(<4 x s16>) = G_ABS [[COPY]]
; CHECK: $d0 = COPY [[ABS]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = G_ABS %0
$d0 = COPY %1(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: abs_v8s16
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: abs_v8s16
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK: [[ABS:%[0-9]+]]:_(<8 x s16>) = G_ABS [[COPY]]
; CHECK: $q0 = COPY [[ABS]](<8 x s16>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<8 x s16>) = COPY $q0
%1:_(<8 x s16>) = G_ABS %0
$q0 = COPY %1(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: abs_v2s32
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: abs_v2s32
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[ABS:%[0-9]+]]:_(<2 x s32>) = G_ABS [[COPY]]
; CHECK: $d0 = COPY [[ABS]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = G_ABS %0
$d0 = COPY %1(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: abs_v4s32
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: abs_v4s32
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK: [[ABS:%[0-9]+]]:_(<4 x s32>) = G_ABS [[COPY]]
; CHECK: $q0 = COPY [[ABS]](<4 x s32>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = G_ABS %0
$q0 = COPY %1(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: abs_v4s8
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: abs_v4s8
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[ABS:%[0-9]+]]:_(<8 x s8>) = G_ABS [[COPY]]
; CHECK: $d0 = COPY [[ABS]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = G_ABS %0
$d0 = COPY %1(<8 x s8>)
RET_ReallyLR implicit $d0
...
---
name: abs_v16s8
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: abs_v16s8
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[ABS:%[0-9]+]]:_(<16 x s8>) = G_ABS [[COPY]]
; CHECK: $q0 = COPY [[ABS]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = G_ABS %0
$q0 = COPY %1(<16 x s8>)
RET_ReallyLR implicit $q0
...
|
