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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: legal_v4s32_v2s32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: legal_v4s32_v2s32
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0
; CHECK: $q0 = COPY [[INSvi64lane]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s32>) = COPY $d1
%2:fpr(<4 x s32>) = G_CONCAT_VECTORS %0(<2 x s32>), %1(<2 x s32>)
$q0 = COPY %2(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: legal_v8s16_v4s16
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: legal_v8s16_v4s16
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0
; CHECK: $q0 = COPY [[INSvi64lane]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = COPY $d1
%2:fpr(<8 x s16>) = G_CONCAT_VECTORS %0(<4 x s16>), %1(<4 x s16>)
$q0 = COPY %2(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: select_v16s8_v8s8_undef
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: select_v16s8_v8s8_undef
; CHECK: liveins: $q0
; CHECK: %a:fpr64 = IMPLICIT_DEF
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: %concat:fpr128 = INSERT_SUBREG [[DEF]], %a, %subreg.dsub
; CHECK: $q0 = COPY %concat
; CHECK: RET_ReallyLR implicit $q0
%a:fpr(<8 x s8>) = G_IMPLICIT_DEF
%b:fpr(<8 x s8>) = G_IMPLICIT_DEF
%concat:fpr(<16 x s8>) = G_CONCAT_VECTORS %a(<8 x s8>), %b(<8 x s8>)
$q0 = COPY %concat(<16 x s8>)
RET_ReallyLR implicit $q0
...
---
name: select_v16s8_v8s8_not_undef
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $d1
; CHECK-LABEL: name: select_v16s8_v8s8_not_undef
; CHECK: liveins: $q0, $d1
; CHECK: %a:fpr64 = COPY $d0
; CHECK: %b:fpr64 = COPY $d1
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %b, %subreg.dsub
; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], %a, %subreg.dsub
; CHECK: %concat:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0
; CHECK: $q0 = COPY %concat
; CHECK: RET_ReallyLR implicit $q0
%a:fpr(<8 x s8>) = COPY $d0
%b:fpr(<8 x s8>) = COPY $d1
%concat:fpr(<16 x s8>) = G_CONCAT_VECTORS %a(<8 x s8>), %b(<8 x s8>)
$q0 = COPY %concat(<16 x s8>)
RET_ReallyLR implicit $q0
...
|
