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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: return_address_already_live_in_copy
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$sgpr30_sgpr31', virtual-reg: '%0' }
body: |
bb.0:
liveins: $sgpr30_sgpr31
; CHECK-LABEL: name: return_address_already_live_in_copy
; CHECK: liveins: $sgpr30_sgpr31
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY]]
%0:sgpr(p0) = COPY $sgpr30_sgpr31
%1:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
S_ENDPGM 0, implicit %0, implicit %1
...
---
name: return_address_already_block_live_in_copy_not_mf_life_in
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr30_sgpr31
; CHECK-LABEL: name: return_address_already_block_live_in_copy_not_mf_life_in
; CHECK: liveins: $sgpr30_sgpr31
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY]]
%0:sgpr(p0) = COPY $sgpr30_sgpr31
%1:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
S_ENDPGM 0, implicit %0, implicit %1
...
---
name: return_address_no_live_in
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: return_address_no_live_in
; CHECK: liveins: $sgpr30_sgpr31
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]]
%0:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
S_ENDPGM 0, implicit %0
...
---
name: return_address_no_live_in_non_entry_block
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: return_address_no_live_in_non_entry_block
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $sgpr30_sgpr31
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
; CHECK-NEXT: S_BRANCH %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]]
bb.0:
G_BR %bb.1
bb.1:
%0:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
S_ENDPGM 0, implicit %0
...
---
name: return_address_multi_use
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: return_address_multi_use
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $sgpr30_sgpr31
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
; CHECK-NEXT: S_BRANCH %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY]]
bb.0:
%0:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
G_BR %bb.1
bb.1:
%1:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
S_ENDPGM 0, implicit %0, implicit %1
...
---
name: return_address_kernel_is_null
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
isEntryFunction: true
body: |
bb.0:
; CHECK-LABEL: name: return_address_kernel_is_null
; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
; CHECK-NEXT: S_ENDPGM 0, implicit [[S_MOV_B64_]]
%0:sgpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
S_ENDPGM 0, implicit %0
...
|
