1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
|
; RUN: llc -mtriple=amdgcn -amdgpu-set-wave-priority=true -o - %s | \
; RUN: FileCheck %s
; CHECK-LABEL: no_setprio:
; CHECK-NOT: s_setprio
; CHECK: ; return to shader part epilog
define amdgpu_ps <2 x float> @no_setprio() {
ret <2 x float> <float 0.0, float 0.0>
}
; CHECK-LABEL: vmem_in_exit_block:
; CHECK: s_setprio 3
; CHECK: buffer_load_dwordx2
; CHECK-NEXT: s_setprio 0
; CHECK: ; return to shader part epilog
define amdgpu_ps <2 x float> @vmem_in_exit_block(<4 x i32> inreg %p) {
%v = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 0, i32 0, i32 0, i32 0)
ret <2 x float> %v
}
; CHECK-LABEL: branch:
; CHECK: s_setprio 3
; CHECK: s_cbranch_scc0 [[A:.*]]
; CHECK: {{.*}}: ; %b
; CHECK: buffer_load_dwordx2
; CHECK-NEXT: s_setprio 0
; CHECK: s_branch [[EXIT:.*]]
; CHECK: [[A]]: ; %a
; CHECK-NEXT: s_setprio 0
; CHECK: s_branch [[EXIT]]
; CHECK-NEXT: [[EXIT]]:
define amdgpu_ps <2 x float> @branch(<4 x i32> inreg %p, i32 inreg %i) {
%cond = icmp eq i32 %i, 0
br i1 %cond, label %a, label %b
a:
ret <2 x float> <float 0.0, float 0.0>
b:
%v = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 0, i32 0, i32 0, i32 0)
ret <2 x float> %v
}
; CHECK-LABEL: setprio_follows_setprio:
; CHECK: s_setprio 3
; CHECK: buffer_load_dwordx2
; CHECK: s_cbranch_scc1 [[C:.*]]
; CHECK: {{.*}}: ; %a
; CHECK: buffer_load_dwordx2
; CHECK-NEXT: s_setprio 0
; CHECK: s_cbranch_scc1 [[C]]
; CHECK: {{.*}}: ; %b
; CHECK-NOT: s_setprio
; CHECK: s_branch [[EXIT:.*]]
; CHECK: [[C]]: ; %c
; CHECK-NEXT: s_setprio 0
; CHECK: s_branch [[EXIT]]
; CHECK: [[EXIT]]:
define amdgpu_ps <2 x float> @setprio_follows_setprio(<4 x i32> inreg %p, i32 inreg %i) {
entry:
%v1 = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 0, i32 0, i32 0, i32 0)
%cond1 = icmp ne i32 %i, 0
br i1 %cond1, label %a, label %c
a:
%v2 = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 0, i32 0, i32 1, i32 0)
%cond2 = icmp ne i32 %i, 1
br i1 %cond2, label %b, label %c
b:
ret <2 x float> %v2
c:
%v3 = phi <2 x float> [%v1, %entry], [%v2, %a]
%v4 = fadd <2 x float> %v1, %v3
ret <2 x float> %v4
}
; CHECK-LABEL: loop:
; CHECK: {{.*}}: ; %entry
; CHECK: s_setprio 3
; CHECK-NOT: s_setprio
; CHECK: [[LOOP:.*]]: ; %loop
; CHECK-NOT: s_setprio
; CHECK: buffer_load_dwordx2
; CHECK-NOT: s_setprio
; CHECK: s_cbranch_scc1 [[LOOP]]
; CHECK-NEXT: {{.*}}: ; %exit
; CHECK-NEXT: s_setprio 0
define amdgpu_ps <2 x float> @loop(<4 x i32> inreg %p) {
entry:
br label %loop
loop:
%i = phi i32 [0, %entry], [%i2, %loop]
%sum = phi <2 x float> [<float 0.0, float 0.0>, %entry], [%sum2, %loop]
%i2 = add i32 %i, 1
%v = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 %i, i32 0, i32 0, i32 0)
%sum2 = fadd <2 x float> %sum, %v
%cond = icmp ult i32 %i2, 5
br i1 %cond, label %loop, label %exit
exit:
ret <2 x float> %sum2
}
; CHECK-LABEL: edge_split:
; CHECK: s_setprio 3
; CHECK: buffer_load_dwordx2
; CHECK-NOT: s_setprio
; CHECK: s_cbranch_scc1 [[ANOTHER_LOAD:.*]]
; CHECK: {{.*}}: ; %loop.preheader
; CHECK-NEXT: s_setprio 0
; CHECK: [[LOOP:.*]]: ; %loop
; CHECK-NOT: s_setprio
; CHECK: s_cbranch_scc1 [[LOOP]]
; CHECK {{.*}}: ; %exit
; CHECK-NOT: s_setprio
; CHECK: s_branch [[RET:.*]]
; CHECK: [[ANOTHER_LOAD]]: ; %another_load
; CHECK: buffer_load_dwordx2
; CHECK-NEXT: s_setprio 0
; CHECK: s_branch [[RET]]
; CHECK: [[RET]]:
define amdgpu_ps <2 x float> @edge_split(<4 x i32> inreg %p, i32 inreg %x) {
entry:
%v = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 0, i32 0, i32 0, i32 0)
%cond = icmp ne i32 %x, 0
br i1 %cond, label %loop, label %another_load
loop:
%i = phi i32 [0, %entry], [%i2, %loop]
%mul = phi <2 x float> [%v, %entry], [%mul2, %loop]
%i2 = add i32 %i, 1
%mul2 = fmul <2 x float> %mul, %v
%cond2 = icmp ult i32 %i2, 5
br i1 %cond2, label %loop, label %exit
exit:
ret <2 x float> %mul2
another_load:
%v2 = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 0, i32 0, i32 1, i32 0)
%sum = fadd <2 x float> %v, %v2
ret <2 x float> %sum
}
declare <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32>, i32, i32, i32, i32) nounwind
|
